Research And Design On Column-Level High Precision ADC For Image Sensor

In recent years,CMOS image sensor(CIS)has been widely used in various fields,including smartphones,automobiles,industry,and security.CIS technology is rapidly advancing towards larger arrays,higher frame rates,and higher precision.The analog-to-digital converter(ADC)plays a key role in converting photoelectric signals to digital signals,directly affecting the imaging quality.Although ADC research in image sensors has made a lot of progress,there are still many problems and challenges in the compromise of accuracy,area and speed,as well as the optimization of noise,offset and linearity performance.The current mainstream pixel signal processing mode is to adopt the column-level ADC readout architecture,with single-slope(SS)ADC,successive-approximation register(SAR)ADC and cyclic ADC being the typical structures.This thesis focuses on the research and design of a high-precision column-level ADC for image sensors.Through the analysis of various ADC structures and their deformation structures,the advantages,disadvantages and application range of each structure are defined,which lays the foundation for structure selection.The influence of ADC key performance indicators on image sensor performance is analyzed,and the direction of circuit design and optimization is defined.A 12-bit segmented capacitance asynchronous SAR ADC and a 12-bit asynchronous SAR/SS ADC are designed respectively,and the asynchronous SAR/SS ADC is optimized based on the chip test results of the SAR ADC.The main research contents of this thesis are as follows:(1)To address the problem of large circuit area in high-resolution SAR ADCs,a 12-bit segmented capacitance asynchronous SAR ADC with a sampling frequency of 1 MS/s is designed.The entire capacitor array is divided into an 8-bit most significant bit(MSB)subarray and a 4-bit least significant bit(LSB)subarray by using the bridge capacitor,resulting in a92.97% reduction in the number of capacitors.To address the problem of nonlinear distortion caused by high-order capacitor mismatch,a clock-averaging dynamic element matching(DEM)control circuit is proposed.The high two-bit capacitors are evenly divided into three groups of sub-capacitors,and the DEM control circuit is used to change the position of switching subcapacitors for high-bit and second high-bit conversions,thus averaging out the mismatch errors and reducing DC offset and low-frequency noise.Simulation results show that the designed clock-averaging DEM circuit improves the dynamic performance of capacitor DAC.MonteCarlo simulation results show a 37.5% improvement in the robustness of capacitor DAC to process deviation.(2)Based on the 55 nm CMOS process,layout design and chip testing of the SAR ADC are completed.To simplify the wiring complexity,a "C" type capacitor layout is designed to address the difficulty in the layout of the capacitor array’s common centroid and the sensitivity of the bridge capacitor to parasitism.The final ADC core area is 82.4 μm×133.6 μm.After chip fabrication,dynamic and static performance testing is carried out.The results show that the ADC has an ENOB of 8.40 bits,DNL of-0.9/+1.9 LSB,INL of-5.8/+1.5 LSB,and a power consumption of 34.92 μW.Aiming at the performance gap between the test results and the postlayout simulation,the error analysis is carried out by combining the behavior modeling with the test results.A specific error source identification process is proposed.Through spectrum observation and model simulation,the possible source of error and the approximate error range can be located,which provides the optimization direction and ideas for the follow-up work.(3)A two-step hybrid ADC structure combining asynchronous SAR and SS ADCs is proposed.Based on the chip testing results and the performance requirements of the CIS,it is found that high-resolution SAR ADCs face a significant trade-off between area and accuracy.Therefore,an asynchronous SAR/SS hybrid two-step ADC architecture is proposed to address this issue.In order to reduce the complexity of two-step ADC control logic,a control logic switching module is designed on the basis of traditional asynchronous control logic: SAR ADC is controlled by internal asynchronous clock when performing high level conversion,and SS ADC is controlled by counting clock when performing low level conversion.Switching signal generation and switching action are all completed in ADC.An array global calibration method is proposed for comparator offset.The coarse and fine calibration are completed by current compensation circuit and delay adjustable circuit respectively.The calibration stage is controlled by local calibration state transition logic circuit and switch transition logic circuit.Monte-Carlo simulation results show that the offset voltage decreases from 5.98 m V to 0.29 m V.The traditional binary capacitor array is configured into a sub-binary structure,which improves the fault-tolerant and error-correcting capabilities of ADC.The bootstrap switch is optimized for charge injection and body effect using substrate bias control,increasing the ENOB from 13.4 bits to 15 bits.The layout of the asynchronous SAR/SS ADC is designed.The overall area is 57.93 μm × 116.51 μm.The parasitic parameters are extracted and simulated.Under TT conditions,the ADC achieves 10.95 bits of ENOB,DNL of-0.7/+0.9 LSB,and INL of-1.3/+1.4 LSB.