A 10bit 580ksps Successive Approximation Register ADC In 0.18um CMOS Process

Successive approximation register analog-to-digital converter is a common architecture for middle to high accuracy applications which require the sampling rate less than 5MSps. It has the characteristics of low power and small size, thus is widely used in many application fields, such as portable instruments, pen input quantization, industry control and signal collector, etc.In this thesis, we design a fully integrated CMOS SAR ADC for portable systems. It is based on SMIC 0.18um Logic 1P5M process, using Charge Redistribution architecture, thus characterized by low power. We analyze every factor which may affect the accuracy of Charge Redistribution SAR ADC and proposed several conclusions which can also be used in the design of other type high resolution SAR ADC. The circuit design is simulated and layout with EDA tools. The simulation results indicate that the effective accuracy is 9.8bit and the sampling rate can reach 580kSps under different combination of corners and temperature. The area of SAR ADC is 500um×750um.