Low Jitter Clock Receive And Transmit Circuit Design For High Speed Time Interleaved ADC

In recent years,the rapid growth of many emerging areas such as the Internet of Things(IoT),autonomous vehicles,and artificial intelligence(AI)has led to rapid growth in data center and telecom infrastructure bandwidth requirements.The development of backplane receivers based on high speed analog-to-digital converters(ADCs)and associated fiber optic receivers will be the key to next generation communication technologies.For these two technologies,the development of ultra-high-speed analog-to-digital converters(ADCs)is one of the key drivers.Multi-channel parallel-time interleaved ADCs(Time-Interleaved ADCs,TI-ADCs)are commonly used in ultra-high-speed,high-precision ADC solutions.For high-speed time-interleaved ADCs,the quality of the sampling clock will affect the signal-to-noise ratio of the overall ADC circuit and the mismatch of the sampling clock will seriously affect its performance and even cause functional anomalies.Therefore,how to get a clean and stable multi-phase non-overlapping sampling clock is an important research direction of high-speed time-interleaved ADC.Based on the multi-channel structure and working principle analysis of high-speed time interleaved ADC,this paper designs the clock receiving and transmitting circuit of the ADC chip for the system requirements of 12bit 4GSPS time interleaved ADC.A multi-phase clock generation circuit based on shift register is proposed,and the sampling clock is re-timed at the sampling input end of the sub-channel ADC,which eliminates the phase error of the sampling clock between channels introduced by channel mismatch and improve the reliability of the sampling clock.In order to solve the clock signal attenuation and crosstalk caused by the input of the off-chip clock source into the chip,a pre-linear equalizer is designed to filter the signal at the front end of the receiving circuit,and the attenuated clock signal is amplified by the wideband limiting amplifier in the latter stage.The shaping is performed by the digital buffer,and finally the duty ratio adjustment is performed by the duty ratio correction circuit to obtain a main clock signal that satisfies the design requirements.Among them,the design of the broadband limiting amplifier improves the traditional Cherry-Hooper structure,combined with the capacitor peak technology,the capacitor neutralization technology and the characteristic frequency multiplication technology,which greatly expands the channel bandwidth and improves the quality of the received off-chip clock signal.The circuit was simulated by Hspice based on the TSMC 40nm process.The post-imitation results show that the circuit can effectively receive the off-chip 4GHz high-frequency clock signal and generate the multi-phase non-overlapping sampling clock required for the time-interleaved ADC.The total layout area is approximately 0.1368 mm~2and the power consumption is 33.70 mW.At the same time,the duty cycle adjustment requirements and clock jitter requirements are met,the duty cycle error is less than±1%,and the clock jitter is less than 150fs(RMS).