Design Of Time-Interleaved ADC’s Clock Reception And Distribution Network

TI-ADC is widely used in high-speed high-precision ADC solution. TI-ADC can get the maximum conversion speed, better power-speed trade-offs, lower clock network power consumption and decrease ADC metastability. However, in addition to interchannel mismatches and the area penalty, interleaving entails a number of other issues as well: TI-ADC requires multi-phase clock generation and distribution, larger input capacitance results in higher power consumption of the driver.First, this paper introduces the basic principles of TI-ADC, in-depth analysis of the impact of the timing mismatch and large input capacitance on the overall performance of the TI-ADC. In this paper, with the help of master/slave sampling network, we can reduce both pre-driver’s load capacitance and the difficulty of timing calibration.Then, the paper describes the working principle and circuit structure of the clock system. In the clock receiver, using CML clock buffers reduces clock jitter; zero delay buffer delay-locked loop formed by the mixing so that the main sampling clock from the sampling clock timing and alignment; with self-calibrated delay-locked loop we obtain a high accuracy of 32-phase clock, select different phases of the clock do NOR operation so that we get Sub-ADC clock.Finally, with the help of EDA software, the whole clock system is simulated. Simulation results show that, in the 1.2GHz clock input, the clock receiver’s jitter is less than 200 fs, and the power consumption is 26mA; zero-delay buffer delay-locked loop’s frequency range can cover 400 MHz to 1.2GHz; multi-phase clock’s timing error is less than 2.8ps. At 2V supply voltage, the total power consumption of the clock system is 96mW.