Ultra-high-speed Parallel Optical Receiver Circuit Design

With the rapid development of Internet, broad bandwidth is on demand greatly. More and more Internet equipments such as Router, ATM, OXC and DWDM are placed together. Because of ultra high-speed transmission data, very short reach (VSR) optical transmission system is the best choice here both for performance and price considerstations.In the building blocks of VSR transmission system, the pre-amplifier, main amplifier and clock recovery circuit are the critical parts in the receiver dirction.The pre-amplifier plays a critical role in optical receiver. Trade-offs between noise and gain-bandwidth characteristics present many challenges in the pre-amplifier design. Thus it would be very efficient if a mimimum noise and a maximum achievable bandwidth can be obtained concurrently. This paper attempts to slove this problem. An auto gain controled (AGC) amplifier or a limiting amplifier is generally used to realize the main amplifier. The latter one was chosen to realize the main amplifier in our design since it has the features of simple topology, few external components and fast responsibility. A limiting amplifier implemented in TSMC 0.25μm CMOS technology is described. Active inductive loads and direct-coupled technology are employed to increase the gain, broaden the bandwidth, reduce the power dissipation, and keep a tolerable noise performance. Clock recovery circuit is used to extract clock from the output signal of main amplifier. Normally, a phase-locked loop has a very narrow loop bandwidth for good jitter attenuation. In this paper, phase/frequency-locked loop is adopted to achieve wide capture range, small jitter and low power dissipation. A monolithical multi-channel front-end amplifier is realized based on the upper discussion.In this paper, firstly the knowledge about VSR transmission system is introduced; subsequently the design procedure and test results are presented. According to the measurement results, the pre-amplifier, limiting amplifier and clock recovery circuit are suitable for VSR application.