Research And Design Of Clock Duty Cycle Corrector Circuit In High Speed ADC

With the rapid development of digital signal processing technology and communication technology, the requirement of precision and speed of ADC is continually improved. Among the high speed ADCs, the folding and interpolating ADC has become a research hotspot in high speed field in recent years. It can improve the speed of folding and interpolating ADC by using the time interleaving technique. However, with increasing of the frequency of input signal and sampling clock, the duty cycle and jitter of clock on the performance of ADC are more and more crucial, therefore the design of a Duty Cycle Corrector (DCC) circuit which provides a stable 50% duty cycle is particularly important for the design of high speed and high precision ADC.In this paper, the general situation and performance parameters of ADC are firstly introduced, and the effects of clock duty cycle and jitter on the performance of a dual-channel time interleaved ADC are discussed in detail. Then by studying basic principle of the existing DCC structure and key circuit, analyzing advantages and disadvantages of them, the author summarizes a DCC structure applicable to a 10 bit 1GSPS folding and interpolating ADC. The proposed DCC finally uses a fully differential continuous-time integrator as the duty cycle detector, and combination of transconductance amplifier and CML clock buffer as the duty cycle adjuster, to achieve higher operating frequency and higher calibration accuracy. The clock circuit in differential form can effectively reduce switching noise of traditional clock circuit, and improve the ability of common mode rejection. In the paper, detailed analysis of each part of the DCC circuit is introduced and carried out to design a high speed DCC according to the design index, including selection of RC integral constant, circuit design of integrator amplifier, Linear OTA, and clock buffer of each level. By analyzing the detection sensitivity, the transfer function of duty cycle detector and the voltage control sensitivity of duty cycle adjuster, linear model of the DCC is derived, which is conducive to circuit adjustment and stability analysis of the DCC loop.The circuit is simulated based on the TSMC 0.18μm CMOS process, at 1.8V supply voltage, through the Spectre software of Cadence. Simulation results show that the DCC circuit has an operating frequency range of 250MHz～1GHz. When the frequency of input clock is 500MHz, duty cycle range can be corrected is 20%-80%, and accuracy of the output duty cycle is 50%±0.7%. Setup time is less than 2.8μs, and RMS jitter of output clock is about 278fs, which have reached the design requirements.