The Design Of Clock Circuit For Ultra High Speed Time Interleaved A/D Converter

With the rapid development of information technology, a large number of military and civilian products of A/D converters are demanded with speed higher and higher. It’s more and more urgent for the demand of high-speed ADC. For realizing ultra-high speed ADC, a general method is using time-interleaved technology. A/D converter includes circuits of tracking and holding、quantizing、coding and the output circuit, all of these circuits are working successfully under the control of clock signals, so the performance of clock circuit directly affects the performance of A/D converter. Therefore, the research and design of clock circuit of ADC are implemented in the thesis.In the ultra-high speed A/D converter, a sinusoidal signal is always as input clock signal. Input clock is converted to a square wave signal after the low noise amplifier. The duty ratio of output clock cannot be accurately converted to 50% and the clock also has a big clock jitter. Therefore, the thesis designs a clock stabilizer based on full differential integrator to adjust the clock duty ratio and suppress output clock jitter.In time-interleaved A/D converter, the mismatch of sampling time among channel causes spurious signals, thus reduces the overall performance of the A/D converter. There are two ways for calibration phase errors of the sampling clock is proposed in the thesis: one is implemented to produce the sampling clock without phase deviation controlled by the main sampling clock. In order to calibrate the main sampling clock phase error and reduce the sampling clock jitter, an main sampling clock phase auto-calibration circuit is designed. Another is by SPI manual calibration, there are four identical 8 bit current steering D/A converters are used in the design of circuit, each of sampling clock signal phase delay is controlled by a D/A converter independently. The circuit realizes the 4 road sampling clock phase delay adjusted independently.The design of schematic and layout of clock circuit are fabricated in 0.18μm Si Ge Bi COMS process technology. Extracting the parasitic parameters of layout to simulate the clock circuit. The clock stabilizer which has a maximum operation clock frequency of 2GHz can tune the range of input clock duty cycle from 20%~80% to(50±1)% and suppress clock jitter less than 250 fs. The main sampling clock phase auto-calibration circuit can tune the sampling clock phase error from 15 ps to 0.5ps. The sampling clock phase manual calibration circuit can tune the sampling clock phase error from-13.34ps~13.25 ps to 104.3fs. The clock stabilizer and sampling clock phase calibration circuits meet the index of 8 bit 4GSPS time-interleaved ADC. Therefore, the designed circuits of this thesis can be used the system of clock circuit in 8 bit 4GSPS time-interleaved ADC.