Design Of A High-Speed Low-Jitter CMOS Clock Stabilization Circuit

Today, in the rapid development of communication technology and semiconductor industry, as Analog-to-Digital/Digital-to-Analog Converters are used more and more widely, its performance requirements become more increasingly harsh, and studies in this field become deepening. Among them, the performance of the clock system designed for sampling seriously affects the whole functions and performance of an AD/DA Converter. While in this studying field, a stable clock circuit designed for AD/DA Converters is mostly based on phase-locked loop or delay-locked loop. In this context, this paper analyzes the basic principles of phase-locked loop and delay-locked loop. According to the definition and origin of clock jitter and phase noise, this paper gives the explanations of the effect of clock jitter on ADC system. On the basis, a low jitter CMOS clock stabilization circuit is presented in this paper applied in high speed and high precision Pipeline A/D converters.According to the frequency range of the circuit applied, the requirements of stability and power, this paper utilizes the principle of delay-locked loop for design. Generally, the structure of the clock stabilization circuit proposed in this paper is different from the conventional structure of delay-locked loop. Edge detection circuits in this paper are detecting the feedback signal which is constantly on modulation all the time until outputting the needed clock edge, which makes the frequency of output signal followed by that of input signal. The feedback square wave signals act on current source and current sink of the charge pump, then control the charging and discharging current on the capacitor of the loop filter, which causes the accumulating charge changes on the capacitor. After that, the delay time outputted by the voltage-controlled delay circuit is controlled, and this modulation on the delay time is directly reflected on the adjustment of the duty cycle of the output signal, resulting in this feedback loop.Compared with the double-edge modulation, the single-edge modulation is presented in this paper, which could obviously reduce the clock jitter introduced by this clock stabilization circuit itself. It not only saves the overall area of the layout but also reduces the complexity of a circuit. This paper aims at designing some key performance of the charge pump loop which affects the clock stabilization circuit. Due to some problems such as mismatches between the charging and discharging currents in the charge pump loop, which has important effects on the clock performances such as clock jitter and accuracy and size of the duty cycle, this paper uses the combined charge pump and self-biasing current mirror to effectively reduce charge sharing effect and the loss of electricity distribution to a certain extent. Startup circuit based on a D flip-flop can achieve the initialization of the maximum output duty cycle, which can improve the loop lock time. The design of the amplifier is also improved the jitter performance to some extent. Reasonable design for the voltage-controlled delay unit could make overall clock stable circuit achieve the target duty cycle without introducing any reference signal or designing any extra of reference circuits. This not only will essentially reduce the design difficulty and the circuit complexity, but also reduce the power of the circuit. Meanwhile, it is good to inhibit the effects due to some non-ideal factors introduced by process, temperature drifting and the unstable supply voltage which accounts for the duty cycle precision and clock jitter. The application of second-order low-pass filter with miller capacitor is able to reduce the layout area, which can be used simultaneously to reduce the voltage ripples, which will guarantee tradeoff between the stability of the entire clock stabilization circuit and the circuit locking speed.The simulation results in this paper is based on SMIC 65 nm voltage-supply 1.2V/2.5V CMOS Mixed-signal process. The results show that, below 500 MHz input frequency, when the input duty cycle is in the range of 10%~90%, this circuit could achieve the output with 50% duty cycle, its precision within ±0.2% and its locking time is below 200 ns. Through the data processing in Matlab, when the input frequency is 200 MHz, the Peak-to-Peak jitter of the output signal is 1.447 ps, and the RMS jitter is 186.6fs; when the input frequency is 500 MHz, the Peak-to-Peak jitter of the output signal is 1.42 ps, and the RMS jitter is 124.2fs. With 2.5V supplied voltage, the power consumption is less than 1.88 m W.