Research On Design Of The Clock Recovery Circuit For High-Speed SerDes System

With the rapid development of the integrated circuit and multi-core processors,the demand for the commination bandwidth between chips and systems is growing.Due to the limitations of the number of pins and the skew of the clock,the traditional parallel transmission is gradually replaced by the high-speed Serializer/Deserializer(SerDes)technology.For the SerDes system,the attenuation,reflection,and crosstalk caused by the channels are the main factors affecting the signal transmission,so it is necessary to have sufficient knowledge of the channel characteristics to plan the circuit design.In addition,whether the clock and data recovery circuit can recover a high precision and low jitter clock will affect the correctness of the output data directly.This paper mainly solves three problems:1)the modeling of the transmission channels;2)the design of the clock recovery circuit and the duty cycle corrector circuit for the Non-return-to-Zero(NRZ)system;and 3)the design of the clock recovery circuit for the Four-level Pulse Amplitude Modulation(PAM-4)system.Firstly,we propose a physical-based channel modeling method.The backplane channel is decomposed and modeled according to the transmission line theory,the parallel plate theory and the multi-port network theory.A simulation process combining parametric input with intermediate data preservation and reuse is proposed to overcome the shortcomings of full-wave software like long computation time and poor reconfigurability.The experimental results show that our channel simulation tool,compared with the commercial software,has an accuracy error of less than 10%within 30 GHz,while the simulation speed can be increased by two orders of magnitude.In addition,in order to solve the shortage of simulation data,a bit error rate estimation method based on the quadratic fit of the Q factor and complementary error function is proposed.It can calculate the bathtub curve of 10-12 bit error rate,and provide a good performance evaluation criterion for SerDes design.Secondly,we propose a half-rate clock recovery circuit based on Bang-Bang phase detector and phase rotator.The causes of the hysteresis effect of D flip-flop are analyzed,and the expressions and estimated values of the inherent delay are given;the output linearity of the phase rotator is optimized,which can reduce the quantization error of the phase interpolation;the power is also lowered by simplifying the DEMUX.Simulated in different corners of the 65 nm CMOS process,the results confirm that the proposed clock recovery circuit can recover a low jitter clock from 10-16 GHz NRZ data transmitted on different channels.A duty cycle corrector with high operating frequency,wide adjustable range,high accuracy and low output jitter is also designed to calibrate the duty cycle distortion.The corrector operates at 10-16 GHz,and can calibrate the 20%-80%duty cycle input clock into 50%±0.56%.Finally,we propose two clock recovery circuits which can overcome the shortcomings of the PAM-4 signaling such as low signal-to-noise ratio,large inter symbol jitter,and easily affected by non-ideal equalization.One is based on the Bang-Bang structure.The phase detector is composed of biased sense amplifier and double XOR logic,which can sample and judge the multi-level signal correctly and filter the asymmetric edge information.The other is based on the minimum mean square error(MMSE)algorithm which can find out the optimum sampling point.We also propose a novel continuous sampling slope detector and a clock shift criterion.The simulation results show that both circuits work well when the equality of the 25 Gb/s PAM-4 signal is good,while the MMSE structure has a better performance and lower bit error rate than the Bang-Bang circuit if the data is not well equalized.In this paper,we analyze the characteristics of the high-speed serial link channels,design clock recovery circuits and duty cycle corrector circuit for NRZ and PAM-4 signaling,and propose innovative modeling methods,circuit designs,and optimization strategies,which can provide some guidance and solutions for the next generation design of the high speed SerDes system.