Research And Design Of High Precision Low Power SAR ADC

In recent years,with the development of Internet of Things technology and big data technology,more and more devices have connected into the Internet and become part of our daily lives.The Internet is rapidly integrating into our lives and is becoming an increasingly inaccessible part of the world.The smart devices under the Internet are also exploding.According to the latest report,IoT devices have now reached 7 billion and are still growing.Among them,the development of high-tech represented by biomedical,environmental testing,automatic driving,artificial intelligence,5G and other equipment is leading the way in the semiconductor field.ADC is an extremely important part of the semiconductor chip category,and almost all devices require the cooperation of the ADC.According to different types of ADC,it can be divided into pipeline ADC,flash ADC,SAR ADC,Delta-Sigma ADC and so on.This project is mainly based on the traditional SAR ADC structure design,making full use of the simple structure of SAR ADC and high degree of digitization.The main reason for the accuracy of high-precision SAR ADC is that the DAC output linearity of capacitor array is low.Based on this,a new correction method is proposed.Firstly,the detailed model of the current high-precision SAR ADC is modeled,and the advantages and disadvantages of various capacitor array correction methods are analyzed.The effects of various calibration models are compared.At the same time,the model is mathematically verified to determine the consumption under the same conditions.The least resource and better correction method.Secondly,after determining the correction mode,the optimal logic circuit is designed for this correction mode,which minimizes the power consumption of the chip consumed by the digital circuit during the calibration process.Finally,the common problems of high-precision SAR ADCs,such as the clock feedthrough of the sampling switch,charge injection,parasitic capacitance,etc.,are analyzed.Finally,compare the various flip logics of the capacitor array,and determine the appropriate flip mode according to the digital logic resources consumed,the number of bits of the flip capacitor required,and the size of the capacitor.Finally,the various limiting factors are combined,and the SAR structure based on the MCS flipping method and VCO comparator is used.Based on this,a set of all-digital capacitance correction logic is designed,and the performance of the chip is improved by using the front-end self-correction method.The final design of the 14-bit SAR ADC can achieve the effective accuracy of 12.33 bits at 100 kHz through the pre-simulation verification at 0.18 um.Compared with the effective accuracy of 9.81 bits at the time of uncorrection,the device uses less resources and does not increase the power consumption of the chip.In this case,the performance of the chip is improved,and the effectiveness of the self-correction circuit is verified.