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Study Of Self-Calibration Technique For High-Resolution SAR ADC And Design Of Key Components

Posted on:2015-04-12Degree:MasterType:Thesis
Country:ChinaCandidate:P DaiFull Text:PDF
GTID:2348330485996056Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
Compared with other kinds of Analog-to-Digital(ADC), Successive Approximation Register(SAR) ADC possesses the advantages of simpler structure, lower power and smaller area. It is widely used in hand-held devices, mobile terminals and sensor network of the internet of things. With the development of technology, the higher resolution of SAR ADC is needed(beyond 12 bit). However, the fabrication mismatch of CMOS technology makes the resolution of SAR ADC limited around 10-bit. Therefore, to enhance the resolution beyond 12 bit, a improved structure or calibration technique is needed.This work studies both of the structure and calibration technique to improve the resolution of SAR ADC. In the aspect of structure, a main DAC(MDAC) with three segments is proposed. It can satisfy the SAR conversion principle, and not only reduce the area overhead, but also reduce the capacitance mismatches as well as power consumption. In the aspect of calibration technique, a self-calibration technique is implemented which occupies two parts, namely calibration algorithm and calibration DAC(CDAC). Calibration algorithm is implemented as digital circuits which controls the calibration and normal conversion flow. It obtains the mismatch error information in MDAC after power-on. Then according the mismatch errors to calculate calibration codes. Finally, feeding back the calibration codes to compensate the mismatch errors in conversion stage. CDAC consists of several identical sub-DAC arrays in parallel. It can not only enhance the calibration efficiency,but also adjust the resolution and range of calibration. The proposed self-calibration technique can be expanded into other ADC with different resolution by expanding the number of sub-DAC in CDA.The proposed self-calibration method is implemented in a 14 bit, 500 kS/s SAR ADC,and this ADC is manufactured with the Global Foundry Chartered 0.35?m CMOS process.The simulation results show that the proposed calibration method can improve the ENOB from 11.66 bit before calibration to 13.11 bit after calibration at the 219 kHz input frequency.
Keywords/Search Tags:digital self-calibration, split capacitor array, high-resolution, mismatch error
PDF Full Text Request
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