Design Of A 1Ms/s 14-bit SAR ADC Based Oncapacitor Sorting Calibration

As a bridge between the analog world and the digital world,the analog-to-digital converter(ADC)has been widely used in industry.With the rise of wearable devices,the successive approximation register type analog-to-digital converter(SAR ADC)has been widely used because of its low power consumption.The 14-bit SAR ADC is very suitable for communication,image processing and medical equipment,and people's requirements for its accuracy are becoming higher and higher.However,due to process limitations,the capacitance of the SAR ADC is naturally mismatched,and its accuracy is therefore limited.For a 14-bit SAR ADC to achieve high accuracy,it must use a very large area.Various calibration methods have been proposed to calibrate the non-ideal factors of SAR ADC and improve the static and dynamic performance.The calibration method of SAR ADC has always been a research hotspot.This paper proposes a novel calibration method to achieve the calibration of capacitance mismatch.If there is a mismatch in a group of unit capacitors,arrange them from small to large,and then combine them symmetrically,the mismatch between the recombined capacitors will be reduced.The main research contents of this article are as follows:(1)This article analyzes several commonly used SAR ADC switching schemes.Through trade-offs in power consumption,area,and comparator requirements,this article selects VCM-based switching schemes to design SAR ADC.(2)By analyzing the distribution function and probability density function of the order statistics,it is concluded that the probability density of a group of order statistics is symmetric about the Y axis.Therefore,the standard deviation of the recombined elements can be reduced by combining symmetric elements.Applying this conclusion to the capacitor can also reduce the standard deviation of the capacitor.Therefore,this paper proposes a capacitor sorting calibration method.The principle of this method is to arrange the unit capacitance from small to large according to the actual size,and then symmetrically combine to reorganize into a new binary capacitor array.(3)In order to realize the method of capacitor sorting calibration,a capacitor comparison circuit is proposed in this paper to compare the capacitance of two capacitors.This paper also proposes a circuit that can realize the sorting of capacitors.This circuit is based on the switch array structure and can realize the bubble sorting of capacitors.(4)The SAR ADC proposed in this paper uses a time-domain comparator.This article elaborates on the design of the time-domain comparator,and analyze the input offset voltage and input noise of the time-domain comparator.The input offset voltage of the comparator is calibrated by gate voltage modulation,so that it can meet the requirement of the comparator of the 14-bit SAR ADC.8 stages of votalge controlled delay line is used to meet the noise requirements.(5)Using 0.18μm technology,a 14-bit 1MS/s SAR ADC was built in Cadence Virtuoso.The simulation results show that after using the capacitor sorting calibration method,the SFDR of the ADC is increased by about 18 dB,the SNDR is increased by about 10 dB,and the Figure of Merit(FOM)achieves 26.24fJ/conv-step.