High-speed Low-noise Phase-locked Clock Recovery Circuit

Low noise, high speed CMOS clock/data recovery (CDR) circuit design is treated in this thesis.First, a brief introduction of CDR is given. Normal baseband communication coding schemes are discussed. Then, some CDR architectures are discussed. Among these architectures, PLL based one is chosen in this thesis.Second, ring oscillator phase noise characteristic is studied in details. The impact and of power supply / ground noise and substrate coupling noise are discussed. Comparison has been made among the power supply reject property of several oscillator architectures. Then, based on Razavi's research work, deeply analysis on the intrinsic noise sources in ring oscillator is carried on. with thermal noise and flicker noise emphasized. A flicker noise optimization method is presented and verified by simulation. For thermal noise, a new model with non-linearity in count is proposed, and the impact of ring oscillator stage number n and differential pair scale S is discussed. Measurement results meet with the model well.Third, the basic principle of commonly used charge pump PLL is discussed. Its linear settling feature is discussed in s-domain, and the phase margin optimization result in reference [13] is verified. Some discrete time modelling method is discussed and compared. Loop noise transfer function in both s-domain and z-domain is deduced. The long term jilter comes from reference clock and VCO are calculated in z-domain. Based on this result, the principle of loop parameter choice is given.Finally, the design, simulation, and measurement results of prototype chip are presented.