The Key Circuits Design Of High-speed SERDES Interface

With the rapid development of communication technology, SERDES interface is quickly becoming the mainstream of transmission interface development, because it has advantages of high transmission rate, strong anti-jamming capability and low power consumption.8B/10B SERDES is an important structure of it, of which the critical circuits have always been hot spots in research and design. Clock and data recovery circuit and serial to parallel conversion circuit are important parts of the deserializer in 8B/10B SERDES and their performance has direct influence on the quality of signal transmission.In this paper, according to the structural characteristics of 8B/10B SERDES and based on the detailed analysis of the working principle of deserializer and SERDES, we have designed clock and data recovery circuit and serial to parallel conversion circuit, which are used in deserializer. In the design of clock and data recovery circuit, based on the structure of phase interpolation, we have designed phase detector for phase detection, voting circuit for phase judgment and digital filtering, shift register for outputing control words of phase interpolation, phase interpolator for interpolation operation of two phase clocks, respectively. The whole circuit adopts the way of fully digital implementation, phase jitter is small and implementation is easy, which guarantees the correct recovery of clock and data. In the design of serial to parallel conversion circuit, we have designed the tree structure and the shift register structure to realize the data conversion from one way to two ways and one way to five ways respectively, which guarantees the correct conversion from serial data to parallel data.In this paper, under power supply of 1.2V and based on SMIC 65nm CMOS process, we have designed and simulated the circuits using software of Cadence’s Composer. The results show that:the designed clock and data recovery circuit, based on the structure of phase interpolation, can realize phase detection and judgment, clocks interpolation and other functions correctly, interpolation step is 7.1ps, which can be used for clock and data recovery; the designed serial to parallel conversion circuit can realize the conversion from one-way serial data to ten-way parallel data when serial transmission rate is 2.5Gbps, which meets the need of serial to parallel conversion in deserializer.