The Design And Implement Of RapidIO Interface On YHFT-QBASE

The next generation wireless communication standard LTE has been established and begun forward to 4G. The development of base station processor and its system interconnect has become a great challenge to meet the requirements of the new wireless communication standard,. YHFT-QBASE is a high performance fix point digital signal processor which is developed for LTE standard by National Univeersity of Defense technology. YHFT-QBASE adopt the serial interface techniques to supply rapid data transfer which accord with RapidIO specification rev.1.3. Aiming at the need of YHFT-QBASE,this paper has designed the RapidIO serial interface(SRIO).The speed of bus transfer capability increases slower than that of processor performance. This case has made that the transfer capability of system interconnect become one of the bottlenecks to improve system performance. With the development of technology and market, the international interconnect standard——RapidIO(Rapid Input Output Interface) appeared, which is applied particularly for the need of embedded system. The RapidIO interface which aims at serial backboard, chip to chip communication, and application interface which related to serial transmission, has become the best choice of embedded system, particular for the wireless communication area with high transmission band above 10Gbps, low power consumption, and low hardware cost.Firstly, the paper has studied the RapidIO interconnect protocol specification completely, include RapidIO logical and transport layers protocol, serial protocol in physical layer. After the analysis of the need of YHFT-QBASE system interconnect, the functions and overall design scheme of the SRIO are defined. The interface transfers data to DSP by the AXI protocol. A AMBA-SRIO bridge component which is used to transform data between the two protocol has been designed. This paper also designs the functions of SRIO physical layer protocol which include serial protocol layer and physical encoding sub-layer(PCS), and uses serialier/deserialier(SerDes) IP core of Synopsys company as SRIO physical media attachment layer(PMA) to construct the whole SRIO which accord with the RapidIO specification rev. 1.3.Secondly, this paper has analyzed SerDes circuit, which is the critical part of SRIO serial interface, and described its components, work principles and realization, Then the paper particularly has studied the clock and data recovery circuit which is the critical part in SerDes. Having studied the SerDes IP core XAUI PHY and analyzed the function of interface signals of the IP, the function simulation and integration of the IP have been completed.Finally, the paper has finished verification and analysis individually at module and system level for the design, and gived the synthesis results. The results of verification and synthesis indicate that, the interface can complete I/O logic operations, DOORBELL transaction through physical layer 1x/4x transmission, and meet the design requirements of YHFT-QBASE.