| With the rapid ascension of wideband communication and signal processing systems,the demand for high performance D/A converter has dramatically increased during the last decades.Working as an interface between the digital and analog system,the sampling rate,signal bandwidth,static and dynamic performance of D/A converter gradually becomes the bottleneck restricting the overall performance of electronic system.By systematically analyzing the theory nonideal error of current-steering D/A converter,A 14-bit 5GSPS high speed D/A converter has been designed based on 65nm mixed signal CMOS technology.The overall architecture of this D/A converter includes three parts,namely,14-bit 5GSPS DAC core circuit,5GSPS high speed data receiving and synthesis circuit,and 2.5GHz high speed clock receiving and processing circuit.First,the DAC core uses a 4+10 current-steering segmentation strategy.In addition,the high impedance current source,high speed current switch and dynamic element matching(DEM)decoder are used to give the DAC core an excellent static and dynamic performance.Second,the data receiving and synthesis circuit uses a dual channel double-data-rate(DDR)sampling LVDS interfaces to receive the 2.5GSPS parallel data.Afterwards,the data sampling rate rises to 5GSPS with double interpolation filter and data interleaved synthesis.Third,the high speed clock receiving and processing circuit adopts current mode logic(CML)structure to receive the2.5GHz clock signal,and duty cycle adjuster as well as phase-locked loop(PLL)are utilized to recovery 50%duty cycle and reduce the clock jitter.In this paper,a dual-edge output technology is innovatively proposed to accelerate data update rate and broaden the bandwidth of output signals by two-way orthogonal half-period return-to-zero data.In this way,the DAC core updates the output data every half clock period,which can achieve different output modes,such as return-to-zero mode,mixing mode and DDR output mode.In addition,in view of the sensitivity of dual-edge output DAC core to clock duty cycle,a new high speed clock receiving circuit based on CML structure is also proposed in this paper to solve the problem of duty cycle error and crossing voltage deviation.In this way,the duty cycle of output clock signals is kept steady 50%and the error is less than0.5%.According to the layout and wiring strategy,the whole circuit is implemented in 65nm mixed signal CMOS technology.The post-layout simulation results show that the DNL and INL are better than±0.5LSB and±1LSB respectively,the SFDR is better than 77 dBc@100MHz.The chip area is 5*4 mm~2 and the power is 850mW with the 1.8V,-1.5V analog supply voltage and 1.2V digital supply voltage.Finally,further work such as layout optimization and circuit test and perspective research have also been put forward in this paper. |
