Reseach And Design Of High-speed High-resolution Current-steering DAC

Because of the contradiction of the analog world and the booming digital technology, and the status of the bridge between the real world and the digital signal processing system, ADCs and the DACs have been a hot topic since the digital technology comes. ADCs and the DACs limit the speed of the entire system, as the speed of digital processing system improves continually. DACs are worse than ADCS in terms of speed as well as precision. It is very important improve the performance of DACs. The design of DACs becomes more challenged with the decrease of the IC feature size. For this reason, this article design a 12-bit 200 MHz Current-steering DAC based on 40 nm CMOS process.At first, this artcle introduces the basics of DACs. After comparing various types of DACs and combining the DAC design goals, I select segmented Current-steering DAC to be the implementation of the high-speed and high-precision DAC.And then, this artcle researches the main nonideal factors influencing the performance of Current-steering DAC. Through theoretical analysis ang derivation, getting the relationship between the performance of Current-steering DAC and some nonideal factors, such as the current source mismatch、the finite output impedance of the current source and MOS switches. These results can guide the design of Current-steering DAC.At last, this artcle design a 12-bit 200 MHz Current-steering DAC based on 40 nm CMOS process, obtain its layout. Describe the circuit structure of some main modules. Discuss the main rules of Current-steering DAC layout, especially the way to reduce the impact of random and systematic errors to the current sources mismatch.The simulation result is excellent. INL=0.31553 LSB, DNL=0.12422 LSB; 20 MHz input signal frequency, SFDR=78.873 dB, SNDR=71.86 dB, ENOB=11.6462.