Research On High Speed And High Resolution Current-steering Digital-to-analog Converters

With the rapid development of digital signal process, digital-to-analog converters(DACs) play more and more important roles as the bridge between the digital and theanalog domains. Current-steering DACs is commonly used for high speed and highresolution applications as it is intrinsically faster and more linear than competingarchitectures. But inaccurate settled values and nonlinear switching transient bothcontribute to spectral harmonics in these DACs output. In this paper, we research onhigh speed and high resolution current-steering DACs based on circuit design, layoutdesign and calibration method respectively.Firstly, an ideal behavioral model of current steering DAC with7+5segmentationis established. And system test platform on MATLAB is also built to characterize theDAC’s performance. The influence of potential problems on the performance of theDAC is analyzed, such as current source mismatch and their finite output impedance,circuit noise, clock feedthrough and glitch. These error mechanisms are modeled andjoined to the DAC’s model. Then the impact of these nonlinearities on the distortionperformance of the DAC is described by using measures in both the time and frequencydomains. These works could give guidance to DAC’s chip design. In the behavioralmodel, a symmetrical step-shaped switching sequence is proposed to cancel the linearerror and reduce quadratic error. MATLAB simulated results show this methodimproves the linearity of DAC.Secondly,12-bit120Msps current-steering DAC is implemented in TSMC0.13μmCMOS process. In the chip design, we present some practical design considerationsconcerning the layout and choice of circuit structure. The cascaded configuration isdesigned for current cell to get high output impedance. A new switch drive circuit isproposed to reduce output glitch. A current reference with adjustable output currentfrom15μA to80μA is designed. And a temperature compensated circuit for currentreference is used to reduce temperature drift. The simulation shows the temperaturecoefficient of this current reference is26ppm/℃over the wide range of-50℃to150℃when the output current is15μA. To achieve more accurate current reference, an8-bitsbi-directional trimming array with127current levels is proposed. The maximum currenterror is reduced from24%Irefto5.7%Irefafter current calibration. An H-Tree shapedpower wiring is adopted which provides equal distribution of voltages to each current source. Moreover, a high-precision DAC’s chip test platform based on the FPGA is built,including the FPGA implementation of digital signal generator. Measured results showintegral nonlinearity (INL) and differential nonlinearity (DNL) of the fabricated DACare less than0.8LSB and0.2LSB respectively. At120Msps, the spurious free dynamicrange (SFDR) is79dB for sinusoidal signals of5MHz and the power consumption isonly35mW.With the shrinking of process feature sizes and lowering supply voltage, mostconventional improved methods are not suitable for high speed and high resolutioncurrent-steering DACs. In this paper, we discuss some different methods to improveDAC performance in the digital domain. A current source self-trimming and static errorself-calibration are realized respectively based on MATLAB. It has been shown thatthese approaches can be used to achieve high linearity. A new configurable digitalcalibration scheme is presented to compensate dynamic glitch errors in high-speedDACs. At300Msps sample rate for50MHz sinusoidal signal, DAC’s SFDR isincreased by12dB after calibration.In this paper, the key design issues of current-steering DACs for high speed andhigh resolution applications are discussed. But there are also some shortcomings, suchas digital calibration arithmetic is not implemented on DAC chip. These need to befurther investigated in the following studies.