A Study On The Key Techniques Of Ultra-High Speed CMOS D/A Converter

The ultra-high-speed CMOS digital-to-analog converters(DACs)are widely used in mobile communications systems,high-performance radar imaging systems,and high-performance image processing.DAC converter sampling rate as a core technical indicators directly determine the performance of signal processing systems,which is an important frontier and difficult research constraints of VLSI,China's high-speed mobile communications,aeronautics and space,radar and image processing development.Therefore,China's urgent need to carry out high-speed and high-resolution D/A converter key technology research and chip development.This thesis is based on SMIC 0.18?m standard CMOS process to achieve a 14 bit 3GS/s dual-channel current-steering DAC.The DAC uses a 4+10 segment architecture,where the four most significant bits(MSB)with innovative dynamic element matching(DEM)code,to random the static and dynamic mismatch of current sources,and the lower 10 bits use conventional binary decoding.Using high-speed data synchronization technology to receive two groups of 1.5GHz LVDS data,dual-channel interpolation technology is used to achieve the 3GHz data rate;The current switch cell with differential quad-switch fabric,which effectively reduces the impact of the noise of the DAC under high frequency application;The current source uses a two-stage cascode structure to increase the output impedance,reducing the switch feed-through effect on output;The external clock signal up to 3GHz can be received by monostable pseudo-differential ultra-high-speed receiver and the SPI interface to adjust the cross point of the clock to optimize the switch control signal cross point,reducing the DAC's switch output glitch and to improve the overall performance of the DAC.The use of bias replication technology to obtain temperature independent and stable reference current and bias voltage.This design of the 14-bit 3GS/s dual-channel current steering DAC using 3.3V/1.8V dualpower supply,fully differential output structure,the default full-scale output current 20 m A.In the condition of 25? load resistor,differential current is converted to a differential output voltage and then converted to a single-ended output by a transformer,further reducing the effect of even harmonics on DAC performance,resulting in a 1V output voltage swing.Base on the Cadence Spectre simulator and Virtuoso layout editor,completed the DAC overall circuit design and layout of the layout floorplan.The design of the ultra-high current steering DAC was verified by MPW,the whole chip area is 2.62mm×3.14 mm.Under the 3GS/s sampling rate and input100 MHz sinusoidal,the SFDR of the designed DAC obtain 78 d B,the setting time is 2.4ns and the overall power consumption is 527.4m W,which has satisfy the communication system applications in high-speed,high precision,low setting time and low power consumption.