Research On The Design Techniques For High-Speed And High-Resolution Current-Steering Digital-to-Analog Converters

With the development of integrated circuit processes,the characteristic size of transistors continues to shrink and the operating voltage continues to decrease,bringing about the rapid development of large-scale mixed signal integrated circuits,capable of integrating various types of processors,communication protocols,high-speed serial interfaces and highperformance analog circuits onto a single chip to form a large-scale high-performance lowpower So C system,thus bringing about revolutionary development in the field of wireless communication represented by 5G.High-speed high-resolution digital-to-analog converter(DAC),as a key component of RF signal transmission link,is widely used in integrated RF transceiver,radar T/R components and direct digital frequency synthesizer(DDS)systems to realize the conversion of processed digital signals into high-quality analog signals for transmission.The performance of DACs in terms of accuracy,operating frequency and dynamic range has a direct impact on wireless communication systems.Current steering DACs can directly drive the load and achieve high-speed conversion by controlling the current source through complementary switches,and they can achieve a good compromise between accuracy and area overhead through segmented decoding technology.Therefore,it is the preferred architecture to achieve high-speed and high-precision DAC at present.This paper focuses on the design of high-speed and high-resolution current steering DAC.In the aspect of high-resolution design,this paper focuses on the current source calibration technology of current steering DACs.As the resolution of DAC increases,the number of current sources increases dramatically,and the mismatch error of current sources due to random errors of process is one of the main factors affecting the linearity of DAC.This paper presents a theoretical analysis of the influence of random mismatch errors of current sources on static indexed such as INL and DNL of current steering DACs,and proposes a novel digital state machine controlled automatic calibration technique for large-scale current sources to reduce the effects of current source mismatch errors on DAC linearity.Compared with the traditional current source calibration technique,this calibration technique replaces the high-resolution ADC unit commonly used in the traditional calibration technique with a customized high-precision current comparator to achieve the comparison between the current source to be calibrated and the target current.The compensation intervention of the calibration current source is controlled one by one through the accumulation output of a 5-bit counter,and the calibration result can be locked when the counter stops counting.This eliminates the need for fuses and on-chip storage required in traditional calibration techniques,and saves hardware overhead.The calibration technique is implemented in a 16-bit high-precision current steering DAC,and the test results show that the calibrated DNL improves from 3.87 LSB to 1.35 LSB and INL improves from-4.92 LSB to 2.23 LSB.In the aspect of high-speed conversion design,this paper focuses on the research related to high-frequency harmonic energy suppression technology.With the increase of DAC conversion speed,dynamic non-ideal factors such as finite output impedance of current source,switching transient error and data-related inter-code interference gradually overtake the influence of random mismatch error of current source and become the main factors limiting the performance of DAC.This paper presents a systematic analysis of the impact of the above dynamic non-ideal factors on DAC dynamic performance,and focuses on the code-dependent inter-symbol-interference error by proposing a novel dual time-interleaved return-to-zero technique.This technology uses two time-interleaved return-to-zero(RZ)data instead of the traditional single non-return-to-zero data,and replaces the traditional singleswitch control with alternating two-phase switch control to realize the current source output.While effectively reducing data inter-code interference,it avoids the problems of insufficient settling time and output signal energy loss in traditional RZ techniques.Since the switching signal has a fixed zeroing period,this technique can also push the transient error energy introduced during switching to the edge of the first Nyquist domain,which improves the dynamic range of the DAC to a certain extent.This technology has been implemented in a 14-bit 2.8GS/s high-speed current steering DAC,which has been tested to achieve a spurious-free dynamic range of more than 50 d B in the output bandwidth range of more than 1GHz.Based on the above two key technologies,this paper designs and implements a 16-bit 2.5GS/s quad-channel current steering DAC circuit for high-speed DDS devices based on 65 nm CMOS process,and completes the module design and simulation,layout design,overall design,and pre-and-post simulation of the circuit under PVT pull-bias conditions.To solve the problem of high-speed data transmission across the clock domain between DDS and DAC,this paper proposes a novel high-speed timing background calibration technique for real-time tracking of the timing mismatch between high-speed sampling clock and data caused by changes in frequency,temperature and operating voltage,and dynamically adjusts the access delay of the DDS system clock so as to adjust the relative delay of the DDS output data as a whole until it matches the DAC’s first stage sampling clock,guaranteeing the stability and robustness of the device during operation.The testing results show that the spurious-free dynamic range reaches 61.2d B at 2.5GS/s sampling rate and 200 MHz output,and the power consumption is about 800 m W when the four channels work simultaneously.The device can work stably in the temperature range of-40℃~+85℃ and the supply voltage ±5% pull-off condition,which meets the design requirements.