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Research And Design Of High Speed And High Precision Analog-to-digital Converter

Posted on:2013-06-17Degree:MasterType:Thesis
Country:ChinaCandidate:R LiFull Text:PDF
GTID:2248330395450782Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
The Digital-to-Analog Convertors (DAC) as a bridge, linking the digital world to the real analog world,isthe key deviceof the wireless and wire-line communication systems in recent years. To meet the significant development of telecommunication systems, DACs with very high bandwidth and sampling speedsare required; also the SFDR performance is one of the bottlenecks for the communication system. This paper has focused on the improvement of SFDR operating at high input frequency signals with much higher clock frequency.Firstly some basic concepts and architectures of DAC are reviewed, and then some basic concepts of DAC are explained like static and dynamic parameter. Also effects which degrade the DAC performance are discussed. A14bit,1GHz Digital-to-Analog Converter is proposed in this thesis. A segmented (5+5+4) current steering structure is chosen for high speed and high accuracy DAC design is chosen confirmed with system simulation. An interpolation filter is used to pick up the input signal frequency.Design and optimization of DAC blocks are done in details in thesis. More attentions of this thesis are on the design of current source, decoder, synchronization block and switch driver."Always on" current source and the "four-switch" structure are implemented to enlarge the output resistance of current source at both low and high sampling frequency. A segmented "column-row"thermometer decoderwith symmetrical decoding is used to reduce the complex thermometer decoder logic and also the same activate decode strength is guaranteed. Two stage latch structure is designed to reduce finite setting effect of high transited digital signal, also local clock buffer is implemented to avoid data depended clock loading effect. High crossing-point switch driver is put to minimize glitch error.The chip is implemented in TSMC65nm1P9M GP CMOS process, and the core area is1.56mm2. It works at1.0/2.5V mixed power supply and the power consumption is82mW. Differential nonlinearity of (+1.59,-1.26) LSB and integral nonlinearity of (+2.5,-1.06) LSB have been measured. The dynamic performance has been gotten of SFDR=72.39dBc(fsample=250MS/s, fin=5MHz), SFDR=70.05dBc (fsample=250MS/s, fin=121MHz), SFDR=65.06dBc,(fsample=800MS/s, fin=97MHz) and SFDR=64.24dBc,(fsample=960MS/s, fin=57MHz)。...
Keywords/Search Tags:digital-to-analog converter (DAC), current steering DAC, segmentedhigh-resolution DAC, "Always-on" current source, interpolation filter
PDF Full Text Request
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