A 12-bit 1GHz Current-Steering D/A Converter IP Core

In this paper, a 12-Bit 1GHz segmented current-steering D/A Converter IP core is designed with SMIC 0.18μm mixed-signal CMOS technology library. In the segmented architecture with 5+3+4 sub-way, the 5 most significant bits and the middle 3 significant bits are thermometer decoded and respectively through the column and row decoder to control the unit current source matrix, while the 4 least significant bits use binary-weighted current source structure. This paper focuses on the clock circuit module and V-I converter circuit module. A distributed clock, high in drive capability and accuracy, simple in structure and easy to implement, is used. With a wide-swing cascode structure, V-I circuit provide accurate constant current source for the D/A Converter.In the Cadence environment, using Spectre, Verilog-A simulators and Matlab on SUN workstation and computer, circuits-designing and simulations are done. In the 50Ωload conditions, the designed D/A Converter has the output voltage swing of±1V, full-scale current of 20mA, integral nonlinearity error of less than±0.26LSB, differential nonlinearity error of less than±0.4LSB, a settling time of 1.145ns, SFDR = 89.65dB @ Fclk = 500MHz and Fin = 240MHz, 76.62dB @ Fclk = 1GHz and Fin = 480MHz. D/A Converter overall system power consumption is 89.1mW @ Fclk = 500MHz and Fin = 240MHz, 97.2mW @ Fclk = 1GHz and Fin = 480MHz. The effective chip area is about 0.84mm×1.08mm.