High Speed And High Precision Current Steering Digital To Analog Converter Design

Capable of transforming digital code into analog signal,DAC(Digital to Analog Converter)has always been an indispensable part in wireless communication system.The growing demand of higher data transferring rate calls for high speed DAC design.While the band-efficient communication skills designed to alleviate the contradiction between high transferring rate and limited band tend to impose linearity requirement on the DAC design.As we can see,the research to design of high speed and high linearity DAC is of great importance.Owing to its simple structure and ability to drive resistance load,current-steering DAC is a common choice in the field of high speed and high linearity DAC design.But the ever existence of non-ideal effects in circuit limits its linearity.Based on the analysis of the various non-ideal effects existing in the current steering architecture,the design of a 2GS/s 14-bit current steering DAC where the 5 MSBs are thermometer coded and the 10 LSBs are binary coded is presented in this article.DEM(Dynamic Element Match),CAO(Cascade Always On)and centroid switching scheme are used to counter the inherent non-linearity.And the use of quadrature switching enables the time division multiplexing of the DAC,which helps to achieve a sample rate of 2GS/s.To suppress the spectrum spur caused by duty cycle error of the clock under time division multiplexing mode,a duty cycle calibration block is involved in the design.The DAC has been fabricated in TSMC 45nm 1P10M CMOS technology with a voltage supply of 2.5V and-1.2V in the DAC core.After fabrication test has shown that the DAC achieves an OIP3 of 25d Bm within an output frequency range from 100MHz to 900MHz.The DAC occupies an area of 0.7mm~2 and consumes a total power of 276mW.