Design And Implementation Of High-Speed And High-Resolution Digital-to-Analog Converter

With the rapid development of communication and multimedia systems, high-speed and high-resolution DACs are required in many applications. Such as high definition television (HDTV), direct digital signal synthesis (DDS) and wireless transceivers, the dynamic performance of DAC, for example SFDR, is more important and concerned. However, as the speed and resolution of DACs increase, the dynamic performance will be affected by more and more errors. One of the most important errors is the switching transient non-ideal behavior including clock feedthrough effect, asymmetric switching and switching timing errors. In this thesis, a detailed analysis of the impact of these errors on the dynamic performance of the DAC was given and a new current switch was proposed. The proposed current switch improved the switching transient non-ideal behavior with the following features. Firstly, it can operate in a low switching swing. Secondly, it realized the synchronous clock feedthrough compensation without introducing any spurious frequency.Based on the proposed current switch, a 12-bit 1GSamples/s current-steering DAC was presented. With LVDS high-speed interface and 20mA full scale, the DAC adopted 5+3+4 segmented architecture which the 5 most significant bits are thermometer-decoded to control the current source array with 31 cells; the 3 intermediate bits are also thermometer-decoded to control the current source array with 7 cells; the remained 4 least significant bits control the binary weighted current sources directly. The chip was designed and simulated by using TSMC 0.18μm mixed signal technology with the die area of 2.34x2.34mm2. The measured DNL is 0.8LSB, and INL is 0.9LSB. The DAC achieves a 66dB SFDR at 400MSamples/s and 100MHz output frequency.