Font Size: a A A

Study And Implementation Of The Key Design Techniques For High Speed And High Resolution Current Steering DACs

Posted on:2015-02-07Degree:DoctorType:Dissertation
Country:ChinaCandidate:X B XueFull Text:PDF
GTID:1268330425496861Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
The performance of the high-speed and high resolution digital-to-analog converter (DAC) has become the bottleneck of the overall system in the applications such as wire or wireless communications, video signal processing, and direct digital signal synthesis. The current-steering DAC is widely used in high-speed and high-resolution fields because of its intrinsic high speed and driving capability. However, various factors influences the performance of the current-steering DAC, which makes the chip design difficult. This paper mainly focuses on the design difficulties and studies the key techniques which are implemented and validated.This paper systematically analyzes the error sources which impact the DAC’s performance, and further gives qualitative or quantitative analysis on the performance degradation caused by them. These error sources produce both static and dynamic errors which are dominant at low and high signal frequency, respectively. The mainly static error in the DAC is amplitude error, including mismatch error which is related to the technology process and gradient error which is related to the position of the current source. The dynamic errors are mainly timing error, clock jitter, finite output impedance, output variation effect and nonlinear switching transient. Some of them directly generate harmonic distortions on the DAC’s output, and some can cause nonlinear distortion to the DAC through the second-order effects. The total distortion of the DAC is superposition of the distortion caused by these errors, and they are dominant in different frequency ranges. According to the analysis in this paper, the influences on the DAC caused by various error sources can be summarized as follows. The static amplitude error and finite output resistance play the major roles when the input varies from DC to low frequency. With the input frequency increasing, the timing error gradually affects the dynamic performance of the DAC. When the input frequency continues to increase, the errors from the output variation and its second-order effect caused by switching transient will influence more and more on the DAC’s performance. It causes the dynamic performance degradation at a speed of-20dB per decade with the input frequency increasing. When the frequency goes up to very high, the finite output impedance of the DAC is dominant and will cause the performance decline at-40dB per decade.Based on the studies on the DAC’s error sources, this paper gives the corresponding design strategies and schemes including a5+3+4DAC segmentation strategy, a fast solution of the binary to thermometer decoding, a low-column redundant decoding method, a centroid arrangement with gradient compensation of the current sources in the layout array, a way of increasing the output impedance, a design strategy of the switching signal, and a switch driver which is suitable to generate the switching signal with low voltage swing.In addition, a dynamic calibration technique for reducing the timing error is also presented in this paper. The proposed calibration technique employs a time difference amplifier (TDA) to detect and amplify the timing differences between the signal path to be correct and the reference signal path. Then, the timing error is digitalized by time-to-digital converter (TDC) and is further used to control the digital delay line (DDL) to compensate the timing error by adjusting the delay generated by the DDL The calibration technique has a simple structure with less analog circuits which are easy to match in the layout and good for increasing the calibration accuracy. Meanwhile, as the error caused by the calibration circuit is a common value, it will introduce less mismatches between different signal paths. The effectiveness of the proposed calibration technique is validated by the fore and post simulations in this paper.According to the proposed design strategy, a12-bit400MS/s current-steering DAC with intrinsic accuracy is implemented in TSMC0.18μm technology. The DAC uses a5+3+4segmentation strategy. The chip core area is1.44mm2. The measured DNL and INL are both better than±0.6LSB, which validate the proper size selection of the current sources and the effectiveness of the arrangement strategy without any static calibration. When the DAC is operating at400MS/s, the measured SFDR is78.8 dBc at a low signal frequency and66dBc at a high input frequency of98.5MHz. The measured SFDR at Nyquist frequency drops down to50dBc, and the70dBc SFDR bandwidth is about70MHz. The measurement results show that the designed DAC is suitable for high-speed and high-resolution appications.
Keywords/Search Tags:digital-to-analog converter, current-steering, high-speed andhigh-resolution, dynamic calibration
PDF Full Text Request
Related items