14bit High-speed SH-less Pipelined ADC Research

With the improvement of digital process chip and the development of wireless communication technology, the sample rate and resolution of ADC(analog to digital convertor) need to meet the high demand. Fitting well for the high speed and high resolution application, study and design on pipelined ADC are drawing widely attention. SH-less architecture of the pipelined ADC can reduce power, noise and distortion effectively and has already become a research hotspot at present. The SH-less pipelined ADC performance is directly determined by the first stage, therefore the design of first stage circuit is crucial importance for the whole circuit implementation. This thesis focuses on the first stage realization to describe the design of SH-less Pipelined ADC with high speed.The first stage circuit consists of sampling network, sub-ADC, sub-DAC(digital to analog converter), dither injection and residue amplifier. Since sampling network and sub-ADC sample the input signal at the same time, the two parts must exactly match in order to keep the same sampling the input signal in SH-less pipelined ADC. Sub-ADC quantifies the input signal and produces the corresponding output digital codes. The digital codes of sub-ADC are encoded as sub-DAC input.The input signal sampled by sampling network subtracts sub-DAC output and adds dither to get the residues. Residue amplifier amplifies the residues to generate the input signal of subsequent stages. To eliminate the effect of comparators offset voltage, a redundant correction algorithm is employed. The unit capacitance in sub-DAC is increased by encoding the odd and even comparators output in different ways. A known dither signal is injected into the input signal to reduce the DNL(differential non-linear error), which can improve the linearity of ADC effectively. However, the SNR(signal to noise ratio) does not decrease since the output digital codes subtract the corresponding digital codes of dither. An amplifier with high gain wide bandwidth is used to meet the precision and speed of the analog signal processing requirements. Swing scaling technique is adopted in residue amplifier, which not only improves the analog signal linearity of the amplifier output, but also increases the size of unit feedback capacitance.Firstly, the thesis introduces the basic structure of pipelined ADC, and then analyzes the non-ideal error existing in the circuit. The corresponding measures eliminating the error are provided, which contain improved bootstrapped switch, high-speed comparator with offset-cancelled, dither and amplifer with high gain wide bandwidth. Finally, the thesis describes the design of pipelined ADC basic modules and the circuit implementation of improved performance techniques.The proposed ADC layout area is 4.95mm2 in the standard SMIC 0.18μm 1P6 M CMOS process with a supply of 1.8V. The final design in this thesis are shown as follow: the improved bootstrapped switch sampling a 17.578 125 MHz 2VP-P at 166 MSps achieves an SFDR(spurious free dynamic range) of 110 d Bc. The average and the standard deviation of the high-speed comparator offset are 99.55μV and 5.47 m V respectively. Its transmission delay is 438.5ps. The performance of the whole ADC is SNR of 84.606 d B and SFDR of 105.027 d Bc for a 17.700 195 312 5MHz input with an amplitude of-0.913 1d BFS, and SFDR of 58.566 d Bc up to 899.291 992 187 5MHz input. Process corner simulation shows the ADC achieves an SNR of 81.756 d B and an SFDR of 95.502 d Bc on the worst case.