Design Of MDAC For High-speed And High-precision Pipelined Analog-to-digital Converter

In the real world,we are exposed to continuous analog information.While only discrete digital information can be transferred and processed by electronic devices.That’s why we need an Analog to Digital Converter(ADC).As 5G technology is widely used in various fields,electronic devices pay more attention to communication speed and information quality.So the demand for high-speed and high-precision ADCs has become more intense.However,there is a large gap between our country’s level of high-speed and high-precision ADCs and the top international level.At the same time,some Western countries unreasonably imposed chip sanctions against our country.Research on highspeed and high-precision ADCs is of great strategic significance for the development of our semiconductor industry.Pipelined architecture has become the preferred choice for design of high-speed and high-precision ADCs.Multiplying Digital to Analog Converter(MDAC)is the core of pipelined ADC and directly determines the overall performance of ADC.Based on the 28 nm process,this thesis designs a MDAC suitable for high-speed and high-precision pipelined ADC.First of all,from the viewpoint of the basic principles of pipelined ADC,the characteristics and application of different types of MDAC are briefly analyzed;then,further discussions are made about MDAC’s nonideal factors,including IGE,DAC error,memory error,and so on.The theory derivation of the different errors’ effect on pipelined ADC is presented.Next,on the base of 14bit-1.3Gsps-6stage pipelined ADC,combined with the stage-scaling,SHA-less and background digital calibration technology,the requirements of first charge redistribution MDAC are determined.Finally,the circuit design and layout design of MDAC are completed,including the amplifier,DAC capacitive arrays,sampling networks,an input buffer and an reference voltage buffer.Compared to traditional design,the MDAC designed in this thesis still exhibits good performance as the PVT(Process Voltage Temperature)changes.It can be injected into various Dither signals and matched with different error calibration algorithms.The overall layout area of first MDAC is about 391μm×371μm and the power consumption is about 343 m W from 1.8V supply.This thesis presents first MDAC’s simulations after the layout at the sampling rate of 1.3Gsps and the full swing input signal of 1.8V.MDAC can achieve a SNR of 77 d B equivalent to the input of pipelined ADC at 25°C.When the inputs signal frequency is 314 MHz,SFDR is greater than 77 d B and ENOB is not less than 11 bits.After the pipeline ADC calibration model verifies,ENOB can be increased to 11.9bit,and SFDR is greater than 90 d B.