Research And Design Of High-speed And High-accuracy Sample And Hold Circuit Based On 0.18?m CMOS Technology

Sample and Hold circuit?S/H?is a key module in analog circuits such as Analog-to-Digital Converter?ADC?and signal readout circuits,and whose performance directly affects the performance of those analog circuits.Therefore,it is very important to research high-speed and high-accuracy S/H circuit.A high-speed and high-accuracy S/H circuit was designed in SMIC 0.18?m CMOS process.The main work of this thesis includes the following:Firstly,on the basis of analyzing the pricinple of S/H circuit,different structures and performances of S/H circuit was discussed in this thesis.Sampling errors,which was caused by non-ideal effect of sub-circuits including sampling clocks,sampling switches and operational?OP?amplifiers,were discussed,and it would serve as the theoretical basis of circuit design.Secondly,a high precision bandgap voltage reference?BGR?was designed for S/H circuit by adopting V_EB linearized compensation technique and piecewise linear compensation technique in SMIC 0.18?m CMOS process.Simulation results showed that the desinged BGR achieved the temperature coefficient of 0.47 ppm/?in the temperature range from-40?to 125?and the PSR of-60 dB at low frequency.Thirdly,according to these requirements of S/H circuit for these performances of OP amplifier which included gain,bandwidth and slew rate.On the base of discussing performances of different OP amplifiers,a gain bootstrap OP amplifier,which included these circuits of bias circuit,main OP amplifier,auxiliary OP amp and common-mode feedback circuit was designed for S/H circuit by adopting gain booset technology.And,these circuits,which included high-performance CMOS switch,bootstrap switch and two-phase non-overlapping clock generation circuit,were designed.At the same time,considering the trade-off relationship among power consumption,sampling accuracy,layout area and other factors,the size of sampling capacitance was analyzed and calculated.Finally,based on the designed sub-cuircits of S/H circuit and SMIC 0.18?m CMOS process,a kind of S/H circuit was designed by adopting the topology of capacitance flip.Simulaion results showed that the designed S/H circuit achieved the spurious free dynamic range of the output sampling signal of 90.16 dB,the signal to noise distortion ratio of about 76.38 dB and the effective number of bits of about 12.4bit with the input sinusoidal signal of 48.4375 MHz input frequency and 1.2V peak-peak voltage.