Gain Control Sample / Hold Circuit

Nowadays, analog-to-digital converters (ADCs) have great development in process, architecture and performance. The High speed and high resolution ADCs are very popular. As the most important part in ADC, sample-and-hold (S/H) circuit supplys the output signal to the subsequence circuits, its linearity, speed and resolution have impact on the performance of ADC. A gain can be controlled 10-bit 100MSPS S/H system is obtained in this thesis.First of all, base on the theoretical analysis of the sampling system and the comparement of representative S/H structures, an S/H structure which its gain can be controlled is proposed. A syetem clock circuit which generates a set of clock signals with two nonoverlapping phases and a circuit which controls the sampling switches are designed to fulfill the requirement of the S/H structure, and their rising and drop time is less than 280ps.In the process of designing the core circuits, depend on the analysis of the error of sampling switches and distortion theory, a novel high linearity sampling switch with low signal feedthrough effect is designed to eliminate the substrate bias effect and high frequency signal feedthrough .The circuit's feedthrough voltage is reduced by 23.35mV with high linearity. According to the minimum-settling-time (MST) theory and step-response analysis of a second order system, a novel clock feedthrough frequency compensation method is applied to a Folded -Cascode operational transconductance amplifier. The power consumption is not increased, but the response time of the sampling system is increased by 22.7%.The sample-and-hold circuit is simulated by Cadence EDA software with standard SMIC 0.35μm Si CMOS process model. The simulation shows that in the two different gain conditions, 327.043μV of gain error and 4.2ns settle time can be achieved at 100 MHz sampling rate, when with 49.21875MHz input sinewaves. When the circuit is working in the gain of unit, SFDR is 68dB, when working in the gain of two, the SFDR of the circuit is 68dB. And the power dissipation is 35.2mW.Therefore, the gain can be controlled sample-and-hold circuit fulfills the requirements of 10-bit 100MSPS pipelined ADC.