Research And Design Of Sample-and-hold Circuit For Pipelined ADC

Pipelined ADC has a reasonable trade-off between speed and solution,and has been widely applied in communication,military and other fields.The sample and hold circuit is the first level circuit of Pipelined ADC,and which directly determines the performance of ADC.Therefore,it is important to research high-speed and high-precision sample and hold circuit.So,a sample and hold circuit is designed for a 14 bit 100 MS/s pipelined ADC in SMIC 0.18 ?m CMOS process in the thesis.The thesis including:Firstly,on the basis of the analysis of the basic principle and basic structure of the sample and hold circuit,two different structures of sample and hold circuits are discussed in this thesis.Then,this thesis discusses the characteristics of the time and frequency domain of the sample and hold circuit and the error source.In order to reduce the noise and the design difficulty of operational amplifier,capacitor flip-around sample and hold circuit is applied in this thesis.Secondly,adopting the techniques of VBE linearization compensation and piecewisecurvature compensation,a high-order temperature-compensated bandgap reference(BGR)is designed for sample and hold circuit in this thesis.Compared to traditional first-order BGR,the designed high-order temperature-compensated BGR achieves performance of a low temperature coefficient and a low line regulation.Simulation results show that the designed BGR achieves the temperature coefficient of 0.65 ppm/°C in the range of-55°C to 125°C.Then,on the basis of analyzing the principle and performance indicators of operational amplifier,a high-performance fully-differential gain-boost operational amplifier is designed for sample and hold circuit.In order to optimize the accuracy and stability of the common mode feedback circuit,a improved continuous time common mode feedback circuit is designed in this thesis.Considering the noise,power consumption and layout area of the sample and hold circuit,the value of sampling-capacitance is calculated and selected.And,a bootstrap-switch and a two-phase non-overlapping clock are designed.Finally,based on the designed function modules,a sample and hold circuit is designed and verified through simulation.Simulation results show that the sample and hold circuit achieves the SNDR of 76.8 dB,SFDR of 89.9 dB and the ENOB of 12.47 bit.