The Research And Design Of High Speed Sample And Hold Circuit Of Pipelined ADC

As an important unit of Pipelined Analog-to-Digital Converter, Sample-and-Hold circuit is always given more attention by R&D whose major is high speed and high resolution pipelined ADC. It is in the front of the ADC. The setting error and setting speed are the most important parameters of the Sample-and-Hold circuit which affects the resolution and speed of the whole pipelined ADC directly. Based on SMIC CMOS 0.18μm and 1.8V power supply process, A Sample-and-Hold circuit of 1V FS(full-scale), 10bit, 180MHz pipelined ADC is researched and designed. In order to get the 9 ENOB, with 89.20MHz FS sinusoidal input and 178.57MHz Clock signal input, the SNR of this Sample-and-Hold circuit must be higher than 59dB and the SNR of ADC must be higher than 56dB.In this paper, the function and importance of the Sample-and-Hold circuit in pipelined ADC are introduced. The Sample-and-Hold basics are described. The mode of sampling and the mode of holding are analyzed carefully. In sampling mode, charge injection and non-linearity of switched-resistor are researched; In holding mode, the math model of setting time is set, and the error source of the operational amplifier and the structure of the operational amplifier in common use are introduced. Following the research of the Sample-and-Hold circuit, the Flip-Flop Sample-and-Hold circuit and the module of the circuit is designed, including operational amplifier, bias circuit, CMFB(Common Mode Feed Back), bootstrap switch and clock generator. After the schematic is finished, the layout of the circuit is designed.Hspice simulation shows that the setting time is 1.67ns within 0.5mV setting error. The Sample-and-Hold circuit is applied in 10 bit 180MHz pipelined ADC, with 89.20MHz FS sinusoidal input and 178.57MHz Clock signal input, the SFDR of Sample-and-Hold circuit is 77.3dB. Simultaneously, the ADC is also simulated with Hspice. The result shows that SNDR is 56.50dB, SNR is 6.86dB, THD is -67.51dB and SFDR is 69.82dB, which reach the demands of ADC.