The Design Of A Sample And Hold Circuit For Pipelined ADC

With great improvement in the process speed of digital circuits, how to sample the analog signal as quickly as possible is a key point of a system on processing speed. The sample-and-hold circuit, which is the port that connects analog part to digital part, has decides the speed and accuracy of the whole ADC. As an important unit of pipelined analog-to-digital converter, sample-and-hold circuit is always given more attention by R&D whose major is high speed and high resolution pipelined ADC. Based on Chartered 0.18um CMOS process and with a 1.8V power supply, a sample-and-hold circuit with the FS (full-scale) differential voltage of 2V, which could be used in a 14 bit, 100MHz pipelined ADC is researched and designed.This paper first introduces the significance of the sample-and-hold circuit for a pipelined ADC. The basic principle of the sample-and-hold is described, and the non-ideal effects of switch and parameters of the operation amplifier are analyzed carefully. Following the theoretical analysis and system requirements of the sample-and-hold circuit, the charge-transferring sample-and-hold circuit and the module of the circuit is designed, including switched-capacitor selection, bootstrap switch, gain-boosted operational amplifier, bias circuit, common mode feedback, after the schematic is finished, the layout of the circuit is designed. As two-phase non-overlapping clock is necessary in the process of sample-and-hold, two-phase non-overlapping clock generator circuit is designed in this paper.Finally the results, which are simulated by Hspice and Spectre, are given. The results show that the output signal of the sample-and-hold is ultimately between 999.97mV to 1.00003V when the differential voltages of input are±0.5V and the frequency of clock is 100MHz. The deviation from ideal output voltage is only 0.03mV, which means that the circuit has matched the accuracy of 14bits. When a sine signal with 1V common mode voltage, 0.5V single port magnitude and 48.83MHz frequency is non-correlation sampled by the circuit, the SFDR is 94.9dB and the SNR is 91dB. The result has indicated that such the designed sample-and-hold circuit could satisfy the requirements of ADC.