Design Of A 12 Bit Pipeline ADC

As an interface circuit of analog signal and digital signal, Analog to digital converters get more and more important with the digitalize of circuit system. This thesis submitted a design of 12 bit pipeline analog to digital converter. We did much work in the system architecture design and the transistor level module circuit design. The purpose of this thesis is design a 50Msample/s 12 bit resolution pipeline ADC . A ten stage pipelined architecture was used in this design .The first stage is an 4 bit flash sub ADC, followed by eight stages 1. 5 bit per stage sub ADC and an 1 bit flash ADC. These ten stages formed the ADC core. We accomplished the sub module circuits design, such as high resolution sample and hold circuit, high gain wide bandwidth operational transconductance amplifier ,low offset voltage,low power, high speed comparator, 1.5 bit per stage sub ADC, digital correction circuit, clock stabilization and generation circuit , the trasistor level band gap reference voltage with output buffers and current source reference circuit.This design was tape out based on CSMC 0.5um 2P2M CMOS process. The simulation and optimization of circuit is accomplished and the simulation results are obtained with Cadence Spectre. The simulation results show that the circuit can get 12 bit resolution . The highest sample rates can be 50MSample/s. The test results show that the requirement of the static performance of circuit units can be well achieved. This circuit can be used in the fields of video and audio instruments and the sample of intermediate frequency transceiver of communication.