Study Of Sample-and-Hold Circuit Based On Pipeline ADC

Based on the requirements of high speed and high resolution Pipelined ADCs, a 8-bit 50Msps Sample-and-Hold (S/H) circuit is designed, while the important cells of the S/H circuit are studied in detail, including three Sampling-switches,a Sample-and-hold Amplifier,a Clock-control circuit and Reference circuit.In order to cancel the Charge Injection effect, the bottom plate sampling technology is used in the Sample-and-hold circuit, and a special Clock-control circuit is designed. A Sample-and-Hold Amplifier is designed to improve the Signal-to-Noise Ratio (SNR) and the linearity of S/H. Furthermore, the dummy switch technology is used in the sampling switch to eliminate the effect of clock feed-through.The whole design is based on CSMC 0.5um 2P3M mixed signal process, including schematic simulation and layout design. The optimization technologies of the layout are used to reduce the mismatch of the devices, such as common centroid, root device and dummy device method.As result of pre-simulation, the dc gain of the amplifier is 81.35dB; the setup time of the Sampling-switch is less than 2ns, the On-resistance is less than 505Ωand the Off-resistance is more than 400GΩ; setup time of the S/H circuit is 9.1ns with 8-bit resolution.The post-simulation results are similar to the pre-simulation results.