Wireless Communications Adc S / H Theory And Circuit Design

The wireless communication and digital signal processing technology has rapidly been developing. As the connection between the analog and digital signals, the Analog to Digital Converter (ADC), is moved to the high-frequency side, so the requirements on the speed and accuracy of ADC are raised. In the ADC circuit, the Sample and Hold (S/H) module is one of the dominant factors to determine the speed and accuracy of ADC, so new development opportunities for high-speed, high-pricision ADC and wireless communications will be created by the research and innovation on the S/H circuit.In this thesis, stemming from S/H basic theory, the difficulties and related technical methods of achieving high-performance S/H circuit were researched and discussed from areas which are S/H circuit topology, sampling switch, common mode feedback and amplifier. At the same time, the S/H circuits that adopt gain boosted amplifier and three stages amplifier were designed, which will be applied for a pipelined 14Bit, 100MHz ADC and provide high-pricison and high-linearity sample signals for the pipelined configuration.According to characteristic of S/H circuit in time domain and frequency domain, the relationship between the S/H circuit topologys and setting up time was researched and the parameters of each module in the S/H circuit were deteminted. Simultaeously, no-ideal model of switch was drived and subsidiary circuits were adopted to enhance the performance of sampling switch. In the application of gate voltage bootstrap circuit dirving large size sampling switch, the attenuation associated with the input voltage was reduced by diminishing circuit branch at the gate node of the sample switch and increasing bootstrap capacitance. At the same time,the method to eliminate the step of common mode feedback voltage was proposed and the jitter of common mode voltage in the amplifier was suppressed. In order to design high-performance gain boosted amplifier, high order small signal model of high-bandwidth gain boosted amplifier was established. Complex zeros and poles of high-bandwidth, high gain, large capacitive load gain boosted amplifier were analyzed, which would provide theoretical references for the design of gain boosted amplifier.Basing on the 0.35μm 3.3V CMOS process, the modules in the S/H circuit that adopted gain boosted amplifier was simulated. At the same time, the problems found during simulation and the solutions to the problems were analyzed and expounded. The gain boosted amplifier driving 2×6pF capacitive loads was designed and achieved 110dB open-loop gain with 1GHz unity gain bandwidth, 65°-phase margin and 72.6mW power sonsumption. Under the test condition of single-ended input range V_PP 500mV, double-ended input range V_PP 1V, the S/H circuit that adopted gain boosted amplifier attained SFDR -112dB at the Nyquist frequency. At last, the layout of S/H that adopted gain boosted amplifier was designed.Combined with miller capacitor feedback compensation and No Capacitor FeedForward compensation (NCFF), the steps to design multistage amplifier and three stage amplifier that meet the requirements of S/H circuit in this paper were proposed. Some technical problems will happen, when multistage amplifier is adopted in the S/H circuit, like several zelo-pole doublets exiting in the GBW, the setting of common mode voltage and crosstalk between the input and output of feedforward stage. In this thesis those problems were simulated and researched, which would provide reference to adopt multistage amplifier in the S/H and other switched-capacitor circuits. The three stages amplifier driving capacitive loads 2×6pF was designed and achieved 103dB open-loop gain with 1GHz unity gain bandwidth, 90°phase margin and 47.85mW power consumption. Under the test condition of single-ended input range V_PP 200mV, double-ended input range V_PP 400mV, the S/H circuit that adopted three stages amplifier attained SFDR -95dB at the Nyquist frequency.The result of simlution shows that S/H circuit adopted the gain boosted amplifier and three stages amplifier all meet the requirements of 14Bit, 100MHz ADC.