The Design Of A Sample And Hold Circuit For Pipelined ADC

The miniaturization and diversification for portable multimedia systems and mobile internet terminal devices, need the internal chip more integration and rapidly improvement in the operational performance of IC(Integrated Circuit).Thus, the power comsumption is ask for lower. At the same time, with the continued down-scaling of device sizes and the widly used in system-on-a-chip(SoC), Mixed-Signal Integrated Circuit becomes more and more common. In order to reduce power comsumption and the electric fields that accompany device decreasing, it is important for analog circuits to operate from reduced supply voltages. Howerer, decreaseed supply voltage limits the achievable dynamic range and mandates lower noise of analog circuits, it is contradicted to high dynamic range and low noise that are augmently demanded in wireless and communication applications. Thus, the design of analog circuits naturally comes with the challenge to maintain the desired design levels of performance as the supply voltage is lowered. ADC is widly used in Mixed-Signal IC. For this reason, designing high performance analog-to-digital converters(ADCs) that work with a low voltage and low power consumption is also a challenging job.Sample and Hold circuit is a key functional block of pipelined ADCs. As S/H circuits locate in the front portion of pipelined ADCs, their accuracy and setting speed affects directly the highest resolution and speed of the whole pipelined ADCs. So the research focus of this paper is mainly on the design of a Sample and Hold circuit based on SMIC 0.18μm MS/RF 1P5 M CMOS technology, which is completely compliant with 12 bit pipelined ADC design standard. The circuit consists of several modules, such as fully differential gain-boosted folded cascode opamp, bootstrapped switches and two non-overlapping clock generator and so on.The S/H circuit designed has been simulated at 50MS/s sampling rate using Cadence IC614 Spectre simulator. SHA simulation results show that with a 1Vpp 2.587890625 MHz sinusoidal input signal, the simulation result of the 1024 points Fast Fourier Transform(FFT) of the output voltage shows that the spurious free dynamic range(SFDR) is 68.59 dB, THD is-80.57 dB,SNR is 79.14 dB,SNDR is 71.17 dB,ENOB is 11.53 bit,which satisfies the requirement of 12 bit 50MS/s pipelined ADC standard.