Low-power High-performance Research And Design, Sample And Hold Circuit

Nowadays, along the increasing market of telecommunication systems and consumer electronic appliances, the Analog-to-Digital converters (ADCs), which are of great importance in modern VLSI digital signal processing systems, have got great development in process, architecture and performance, and are developing towards higher sampling rate, higher resolution, and lower power consumption. As the key cell of ADCs, the linearity, power consumption, speed, and resolution of the sample and hold (S/H) circuit affect the performance of the whole ADC directly.This thesis studies the academic models and corresponding circuit implementations for high speed, high resolution S/H circuits. They cover the S/H architectures, sampling switches with error sources, optimization on settling features of S/H, and layout-drawing technical. Finally, a 12bit 100MSample/s S/H circuit is designed based on SMIC 1.8V 0.18μm mixed-signal CMOS process. The details include:1) The main architectures of S/H circuits are discussed, and it specifies that the switched-capacitor close-loop flip-over S/H topology can achieve 12bit 100MSample/s performance under sufficient feasibility and reliability.2) .Equivalence circuit models are established for the single MOS switch and the bootstrapped switch, with studying on the nonideals of them, such as charge injection, nonlinear analog bandwidth and sampling moment uncertainty. For the simple S/H circuit, the harmonic, which is introduced by the nonlinear conducting resistance of two kinds of switches, is analyzed and deduced carefully. And a double-side bootstrapped CMOS switch is designed, in which buck-effect is reduced.3) Mathematic model of the flip-over S/H circuit is established, which studied the factors affecting the large-signal settling behavior and the small-signal settling behavior of S/H. The relationship among settling time, feedback factor, poles of the OPA, bias current, signal swing, and setting accuracy is deduced. For a setting time of 3ns, the bias current of OPA is deduced regarding the former relationship. The gain-boosted folded-cascode architecture has been chosen for the OPA. The gain and the GBW, as well as the phase margin of the OPA are designed to achieve minimum setting time. 4) Based on SMIC 1.8V 0.18μm mixed-signal CMOS process, a 12bit 100MSample/s S/H circuit is designed with Hspice simulation environment and Virtuso layout tool.