Research On An 8-bit 250-MSPS Sample And Hold Circuit

In recent years, the architecture, process and performance of A/D converter have gained great progress; A/D converter is developing towards high-speed and high-precision. Sample and hold circuit is an indispensably important circuit block, which palys the role of sampling a given analog signal and then holding the sampled signal for a certain time to be processed by the following circuits. The performance of sample and hold circuit determines the performance of the whole A/D converter,whose design is a very important phase in the design of the whole A/D converter.the research of dissertation is focus on the existing problems of sample and hold circuit with the purpose of developing high-speed and high precision sample and hold circuit.Firstly, based on the investigation and reading of a large number of literatures,the current development of A/D converter at home and abroad is compared and analyzed in detail, pipeline A/D converter is explained,simultaneously , the research and development trends of sample and hold circuit is also introduced at length.Secondly, Based on the detailed analysis of the operation of sample and hold circuit,several blocks of sampling switch, sampling capacitor and operational amplifier to be used in 8-bit 250Msample/s Pipeline A/D converter are designed .the error sources inherited from sampling switch are analyzed in the designed of sample and hold circuit,and the errors inherited from sampling switch are minished by using appropriate timing,with the respective advantages of MOS FET and Bipolar transistor,a two stage fully differential BiCMOS operational amplifier is designed and switched capacitor commom mode feedback circuit is used to stabilize output common mode voltage of the fully differential BiCMOS operational amplifier, a comparision between two architecture of sample and hold circuit is performed and the architecture of fully differential charge transfer is determined finally to be employed.The sample and hold circuit is finally simulated with the PDK provided by standard 0.35μm BiCMOS process and cadence tools. The sample and hold circuit is simulated under the conditions of power supply of 3.3V,input sinewave with amplitude of 1Vp-p and frequency of 121.09375MHz,the simulated results show the settling time is less than 0.73ns and dynamic specification SFDR is 75dB.It is demonstrated by mesuremed results that the designed sample and hold circuit is sufficient for specification requirements of A/D converter with 8-bit and sampling frequency of 250MSPS. The designed sample and hold circuit can be used to 8-bit 250Msample/s Pipeline A/D converter.