Design Of A Sample And Hold Circuit For Pipelined ADC

Analog-to-digital converters (ADCs) become the important building block in manyelectronic applications, because they are the interface between analog circuits anddigital circuits. The modern advanced electronic systems get fast development in recentyears. Consequently, more ADCs are needed to be produced and high quality should beguaranteed. The Pipelined ADC structure has been universally adopted due to thecharacteristics of high speed and medium-resolution. As a key functional block ofpipelined ADCs, Sample-and-Hold(S/H) circuits have attracted academic and industrialattentions. As S/H circuits lie in the front portion of pipelined ADCs, their accuracy andspeed affects directly the resolution and speed of the whole pipelined ADCs.Based on TSMC0.13um1P8M standard CMOS (1.2V) process, this paperimplements a S/H circuit used in12bit pipelined ADC. Firstly, we introduce thefundamental theories and the main specifications of the S/H circuit, and also analyze thedifferences between two S/H structures. Then, based on the systematical specificationsof the pipelined ADC, we adopt the charge-transferring structure in the S/H circuit. Next,we determine the size of sampling capacitor in consideration of the quantization noiserequirements, the size of the switches in consideration of the sampling time, and thestructure of operational amplifier and related design criterions in consideration of signalsettling error and accuracy error. Finally, we implement the layout design of the S/Hcircuit, and conduct chip level verification test.With10.023MHz FS sinusoidal input and39.936MHz clock signal input, thesimulation results show that the SNR of the S/H circuit is80.0327dB, SFDR is77.0770,and THD is-76.3557. Besides, the test results show that the Pipelined ADC adoptingthis S/H circuit realizes the basic functions, and achieves good characteristics of THDand SFDR.