.10 Bits 100msps Pipelined Adc Adopted Paul And Clock Circuitry And Design

High-speed and high resolution ADCs find wide application in communication systems. This dissertation studies system level simulation of 1.5b/stage pipelined ADC, and designs the typical unit circuits of 10bits 100MSPS pipelined ADC which are sample-and-hold circuit and clock circuit. In the simulation of system level with Matlab tool, the paper discusses the influence of offset voltage and gain error to output range of pipelined stages. And it proves subDAC reference error produce non-monotonicity and missing code, so capacitor mismatch calibration technique is needed in order to reduce subDAC reference error. The results of sample-and-hold circuit and clock circuit are based on circuit level SPICE simulations in Cadence with SMIC provided 3.3 Volt single supply voltage 0.35μm CMOS standard process model. The thesis studies the MOS switch non-ideal characteristics, and designs a full differential sample switch that can eliminate substrate bias voltage. The switch SFDR is 86.2dB. Based on the theory of fast settling behavior, a folded cascode operational Transconductance amplifier OTA with dynamic bias voltage is designed. The simulation shows that the sample-and-hold circuit has 10bit resolution, 80dB SFDR and 30.1mW power consumption for the frequency of 100MSPS. The clock circuit generates a set of clock signals with two nonoverlapping phases, the rising and drop time is less than 200pS. Therefore, sample-and-hold circuit and clock circuit fulfill the requirements of 10bits 100MSPS pipelined ADC.