Research And Design Of An 8bits 250MSPS Pipelined ADC

With the continuous development of application field for wireless communication, portable consumer electronics and automotive electronics, high-performance, low-power, low-cost SOC become main trend of integrated circuit design. The development of SOC requires A/D converter, other analog circuits and DSP to be integrated in a chip. Technology compliable, performance optimized analog-to-digital converter (ADC) is an important building block in SOC. It has been an important research topic to improve the performances of ADCs such as speed, resolution, power dissipation, easy-to-integration by adopting standard CMOS technologies and improving available architectures.This paper presents the design and characteristic analysis of an 8-bit 250MS/s pipelined analog-to-digital converter (ADC). The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock. The former circuit is assembled by a fully differential two-stage operational amplifier. Because of the capacitance bottom plate sampling and fully differential structure, the charge injection effect of switched-MOSFET and the clock feed-through effect induced signal error are eliminated. The linearity, signal to noise ratio (SNR) and conversion-speed of the ADC are improved. Based on 0.35-μm BiCMOS process, the design is verified. When the sample frequency is 250 MHz and input signal frequency is 70.1MHz, the signal to noise ratio (SNR) and spurious free dynamic range (SFDR) can reach 46dB and -63.8dBc respectively. The power consumption of the key A/D circuit is 118mW when the supply voltage is 3.3V.