Design Of Main Circuits In A Low-power Pipelined Analog To Digital Converter

With the explosive development of communication system and digital signal processing technology, the analog to digital converter (ADC), as an interface between analog signal and digital signal, is used more and more widely. ADC is the key cell of application electronic equipment and communication equipment.In recent years, high resolution and low-power are becoming prevailing technologies of ADC due to a great demand of portable electronic products. A low-power 10bit, 1.5bit/stage pipelined ADC architecture in which share-OTA technology is adopted is introduced and analysed in this thesis. Based on its working principles and CSMC 0.6μm CMOS processes, main circuits in the low-power pipelined ADC is designed, including the OTA circuit applicable to share-OTA technology and dynamic comparator circuit. The design of the OTA circuit is cascaded with an improved folded cascode structure worked in the odd classes and a telescopic cascode structure worked in the even classes, using the clock control to satisfy the performance requirements of the sample/hold circuit and residue-gain-circuits. Due to adopting digital calibration techonlogy which can make comparator have much maladjusted error without preamplified stage, the dynamic comparator circuit is used as the key cell of the sub-ADC. It has no DC power dissipation power consumption, meeting the requirements of the low-power ADC. The OTA and comparator circuits are designed and simulated by HSpice software, respectively. The simulation results show that the sample/hold and the odd-class circuits have an open-loop gain of 60dB, the even-class circuits have an open-loop gain of 50dB, the total power comsumption of the OTA is only 4.5mW and the bandwidth is more than 20MHz. All the performances of the OTA satisfy the demands of the low power A/D converter. The power consumption of the dynamic comparator is 3mW and the response time is 35ns, according to the design request. Finally, the layout of the OTA and dynamic comparator circuits is designed by Cadence software, considering the matching of the devices, reducing the parasites and improving the performance of the whole circuit. Then through the DRC and LVS, the preciseness of the layouts and the coherence with the circuits is verified.The OTA and dynamic comparator circuits designed in this paper have the characteristics of low-power and high speed, applicable to the improved pipelined ADC architecture in which share-OTA technology is adopted. Compared with the typical 10bit pipelined ADC, the power consumption is reduced effectively.