Research And FPGA Implementation Of LMS Digital Calibration Algorithm For Pipelined ADC

Analog-to-Digital Converter is a device,which can convert a continuous analog signal to a digital signal,such as temperature,sound and pressure,etc.Due to the innovation and development of digital processing technology,the role of ADC has become so important.The high-performance pipelined ADC with high speed,high accuracy and low power is gradually used in video imaging system,wireless communication system and Active phased array radar,etc.It becomes a hot topic.With the evolution of the process of CMOS,it becomes more and more difficult to calibrate the error of the pipelined ADC through the compensation of analog circuits.The digital calibration technology not only can reduce the design constraints of pipeline ADC which exists on area and power consumption,but also reduce difficulty on designing.The digital calibration technology is becoming a new technology to improve the performance of pipeline ADC.Firstly,this paper introduces the principle of the pipelined ADC,and the errors which exists pipelined ADC analog circuit are analyzed.Based on the transfer function of MDAC,the calibration model is studied and analyzed on Matlab.Then the validity of the model is verified.Based on the above,the Variable Step Size LMS algorithm was simulated with Matlab so that less calibration time could be obtained.The simulation displays that the SFDR increased from 46.32 dB to 82.77 dB,and the ENOB can be enhanced from 7.32 bit to 11.52 bit,the time of calibration and the iterations of the algorithm are significantly reduced.Then by taking the internal structure and resources of Xilinx Virtex-5 FGPA device in consideration,the overall design scheme is presented with Top-down concept of FPGA.Finally,based on above,the test platform was built on Xilinx Virtex-5 ML507.the circuit structure of the calibration system optimized by the pipe-lining design greatly improves the working frequency of system calibration.Then the Verilog code was downloaded in the Xilinx Virtex-5 ML507 board,and the calibration results of the variable step size LMS calibration algorithm confirm that the Effective Number Of Bits can be improved from 7.32 bit to 11.02 bit,and the Spurious Free Dynamic Range rises from 46.32 dB to 80.79 dB.The results show that compared with the basic calibration algorithm,the signed variable step calibration algorithm has better calibration performance.