Design Of High-Resolution Pipelined Analog-to-Digital Converter

High-resolution CMOS analog-to-digital converters with high conversion rate are becoming more paramount in many applications where increasingly complex processing of analog signals is performed digitally. Typically, high-resolution ADCs are based on successive approximation or oversampling architectures, but both of these architectures can not attain high speed of conversion.The pipelined analog-to-digital converter (ADC) is a popular structure for high-speed and high-resolution data conversion and can attain compact area and efficient power dissipation. But due to many non-ideal effects such as finite open-loop gain of Op-Amp, decision-level drift and capacitor mismatches, the pipelined ADCs is generally limited to approximately 8-10 bits of resolution. Although several of these effects can be minimized by good design techniques and stringent attention to details, pipelined ADCs with more than 12 bits resolution will usually require some kind of linearity enhancement techniques. Self-calibration techniques, which measure errors by the converter itself and subtract the code error during the normal operation, can be used to improve the linearity of ADCs.This thesis describes the system design of a high-resolution pipelined ADC. The error sources present in pipelined ADC are identified, and the effects of these errors on linearity are analyzed based on a presented systematic mathematic model. The way in which digital correction eliminates the effect of part of these errors is shown. A novel digital self-calibration algorithm is presented to further increase the linearity of pipelined ADC. A gain-error correction technique is presented to release the requirement of gain of Op-Amp and capacitor mismatch especially for high-resolution pipelined ADCs.