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Study And Design Of Low Power Pipelined ADC With Digital Calibration

Posted on:2014-01-18Degree:DoctorType:Dissertation
Country:ChinaCandidate:Z X XiongFull Text:PDF
GTID:1268330425976737Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Analog to digital converter (ADC), convers the analog signals in real world to digitalsignals which is more convenient for furer processing. It is widely used in the system ofmobile wireless communication、aerospace and medical treatment, etc. In the SOC of theseapplications systems, the ADC resides on the same silicon (system-on-a-chip) with other largedigtal circuits in order to reduce overhead cost. As the bridge between analog domain anddigital domain, the ADC is the indispensable part of SoC. As required by system-on-a-chipintegration and state-of-the-art CMOS technology, analog supply voltage is forced to decrease,following that of digital part. Meanwhile, handset equipments impose stringent requirementon power consumption of the ADC and accelerate the development of high-speedhigh-resolution ADC. To acquire high speed and high accuracy are often needed to increasethe cost of power and area. Therefore, how to achieve high-speed, high-resolutionand,low-power consumption simultaneously becomes a focus.This work focused on the the high resolution and low-power pipelined ADC for dgitalvideo application and modern communication system. Since apperture error was induced bythe conversional SHA-less architecture, to overcome it, a novel SHA-less architecture as wellas circuital level tecniques are proposed for designing high-resolution low-power pipelinedADC. A new digital background calibration with high convergence rate is also proposed toimprove the system accuracy. Two chips were designed and one of the two was measured. Thespecific research contributions of this work include:1. Since the samling rate of pipeline ADC without a SHA can be limited due to theaperture error and other nonideal factors, a novel sample-and-hold amplifier(SHA) merged with the first mutiplying digital to analog converter (SMDAC)architecture is proposed, and to achieve high speed and low power consumptionwithout reset phase.2. To achieve low-power design, opamp-sharing between successive stage andstage scaling-down were adopted. And more, a SC bias current generator wasintroduced to effectively control power consumption for different application. To get rid of the problem of memory effect, the bias-and-input interchangingtechnique for the OTA in the MDAC is proposed.3. A symmetry gate-bootstrapping circuit is proposed for the bottom-samplingswitch of sample-and-hold circuit or SMDAC. It minimizes the effect of switchcharge injection, suppresses the effect of bulk bias, and improves the linearity ofsampling result.4. Digtial background calibration technique for pipelined ADC is investigated, anda novel signal-dependent dithering algorithm is propsed for multibit per stage, inwhich capacitor mismantch and gain error in multibit stage can be calibrated asone error. This scheme shortens the calibration time, reduces the analog circuitdesign complexity, as well as improves the ADC linearity. This calibrationtechnique speeds up the convergence rate of calibration and takes only6224samples to achieve13-bit resolution. It costs1.34s to calibrate this ADC at100MS/s. This calibration algorithm is easy to realize without complicatedmathmatic operation and works at very high speed.
Keywords/Search Tags:analog-to-digital converter, pipeline, sample-and-hold, sample-and-hold circuitmerged with with the first mutiplying digital to analog converter, opamp-sharing, bootstrapping switch, signal-dependent dithering
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