Research And Design Of Two-step Pipelined Analog To Digital Converter Based On Digital Calibration

Two-step pipelined analog to digital converters (ACDs), one of the most popular ADCs, are mainly used in the fields which resolution and speed are both required, such as wireless local area network (WLAN), mobile phone, high-definition television (HDTV), et al.This dissertation introduces the design of a two-step pilelined analog to digital converter based on digital calibration. The ADC combines the pipeline and digital calibration technology of pipeline ADCs' with a basic structure of conventional two-step ADC.Compared with conventional two-step ADC, the performance of the ADC designed in this dissertation has been improved at two aspects. Firstly, digital calibration technology is used to improve the error-tolerance ability and reduce the complexity of circuit design. Secondly, in order to enhance data-throughput and conversion rate, pipeline technology is introduced by using two more track and hold circuits.Important circuits in this system are track and hold circuits, two quantizers and digital calibration circuit. Full-differential open-loop architecture is employed in track and hold circuits, to meet a high speed the system required. Meanwhile, unit-gain amplifier, dummy MOS switch and current mirror with beta helper and emitter degeneration are also used in track and hold circuits to reduce error and increase accuracy. Two quantizers are Flash ADCs, using differential resistor ladder and comparator-network structure. Compared with conventional Flash ADC, the differential resistor ladder quantizier can reduce the integral nonlinearity error and the resistor matching requirement. The comparator designed in the quantiziter can work at a high speed but has a low kick-back noise. Both negative and positive redundance arithmetic are combined in digital calibration circuit. When the redundance overflows positively, thermo-code to binary-code coding mode is used in the first quantizer ADC1 to reduce the complexity of digital calibration circuit.All circuits in this system are designed in 0.6μm BiCMOS technology, with 5V supply voltage, and simulated in Cadence-Spectre. Simulation results indicate that all circuits designed above have good performance and satisfy the requirement of the system. Finaly, the ADC designed in this dissertation can achieve 10-bit resolution at 40MHz sample rate.