Research On Key Technology Of 12-B Pipeline Analog-to-Digital Converter

Analog-to-digital converters,as a bridge between natural signals and machine signals,have been rapidly evolving with the growing demands of society.Since the beginning of the 21 st century,the pipelined analog-to-digital converter has a wide range of applications in nano-scale CMOS technology and has a broad development prospect due to its high resolution,high sampling frequency and simple structure.Therefore,it is important to study the high-resolution,high sampling rate,low-power pipelined analog-to-digital converter.The paper first introduces the structure and working principle of each mainstream analog-to-digital converter,and compares and analyzes the work of full parallel analog-to-digital converter,two-step analog-to-digital converter,successive approximation analog-to-digital converter and pipelined analog-to-digital converter.Principles and advantages and disadvantages.Then the main parameters of the pipeline analog-to-digital converter are analyzed,and the sources of non-ideal factors are studied..Based on the theoretical analysis,the Simulink model of analog-to-digital converter is established and the LMS digital calibration algorithm is implemented.The critical sample-and-hold circuit and Sub-ADC circuit are completed during the circuit design phase.In order to reduce the chip area,the sample-and-hold circuit adopts a flip-type switched capacitor structure,and a new type of bootstrap switch for the sample-and-hold circuit is designed,which reduces the number of capacitors used compared with the conventional bootstrap switch.The comparator used in the Sub-ADC module is a capacitive switch dynamic latch structure comparator,which achieves the goal of high precision and fast working speed.Under the consideration of design difficulty and power consumption,the 12-bit 100 MHz sampling rate analog-to-digital converter model with background calibration algorithm is implemented on MATLAB platform.The simulation results show that the effective number of outputs after calibration reaches 11.4bits.The static parameters are from DNL=-1/+2.3LSB before calibration,INL=-1.5/+2.2LSB,and rise to DNL=-0.31/+0.36 LSB after calibration,INL=-0.2/+0.24 LSB.According to the design parameters given by the MATLAB model,based on the SMIC 40 nm process,the sample-and-hold circuit and Sub-ADC circuit design of the 12-bit pipelined analog-to-digital converter are completed on Cadence's Virtuoso platform.The power supply voltage is 1.2V and the input frequency is In the case of a fully differential sine wave of 4.20 MHz,the effective number of bits of the sample-and-hold circuit is 11.8 bits.Set the input frequency close to the Nyquist frequency point,take the 49.12 MHz fully differential sine wave as the input,and get the effective number of bits in the sample-and-hold circuit output of 11.4bits.The Sub-ADC related circuit simulation shows that the comparator resolution in Sub-ADC is 55?V,which meets the design requirement of 292?V.The output logic of Sub-ADC conforms to the Boolean function,indicating that the design meets the system specifications.