Research On Radiation Hardened By Design Of Low Power SRAM In 65nm CMOS Technology

With the continuous advancement of CMOS manufacturing technology and the rapid development of integrated circuit technology,SoC systems are widely used in many fields such as network communication technology,satellite technology,and wireless sensing technology.In the context of the ever-decreasing size of the integrated circuit process and the gradual improvement of the integration degree,the performance of the integrated system is continuously improved,and the higher requirements of the low power consumption of the SoC system are also put forward.Because of its indispensability,SRAM occupies more than 70% of the memory chips used in many SoC systems.The power consumption will directly affect the power consumption of the entire SoC chip.Therefore,it is more and more important to reduce the power consumption of the SRAM cell through the design of the circuit structure.At the same time,in the SRAM memory cell,when the radiation particles directly bombard the memory cell,the logic value of the memory cell is directly flipped,that is,the Single Event Upset(SEU)phenomenon occurs,which causes soft errors in the circuit.Traditional SRAM memory cells need to be radiation-hardened design to meet their increasingly complex and demanding work environments.This article details the basics of single-particle effects,including related concepts and mechanisms.The circuit-level reinforcement scheme of SRAM unit and related low-power design methods are expounded.A new radiation-hardened SRAM unit is proposed to overcome the shortcomings of previous SRAM design.This paper summarizes the method of designing radiation-hardened SRAM cells for other work,namely the design of radiation-hardened SRAM cell based on stable structure.Based on this,the paper further proposes a new radiation-hardened SRAM cell.Based on the stack structure,the leakage current of the circuit is greatly reduced,and the power consumption of the circuit is effectively reduced.Based on the two stable structures,soft errors caused by the single-event upset can be effectively tolerated.The comprehensive HSPICE simulation shows that compared with the related hardened structure,the power consumption of this structure is reduced by 31.09% on average,HSNM is increased by 19.91% on average,RSNM is increased by 97.34% on average,and WSNM is increased by 15.37% on average.The Static Noise Margin(SNM)shows a excellent stability performance.Although the area overhead increased by an average of9.56%,the average reading time decreased by 14.27%,and the write time decreased by an average of 18.40%,which can meet the needs of high-speed electronic equipment.