Design Of Cmos Radiation Hardened Trigger Based On Micro-nano Process

With the development of integrated circuit process technology,the transistor feature size is getting smaller and smaller,and the influence of ion incidence in the radiation environment is becoming more and more serious,which leads to the single-event effect(SEE)occurred in the integrated circuit more and more easily.Becauseion incidence-induced single-event effect is important forcircuits in aerospace,in order to ensure the normal operation of the system,there are certain requirements for the radiation resistance of the chip.Based on the research of single particle effect technology,this paper proposes an improved D flip-flop against single-event effect and single event transient(SET)by which storing the data in different nodes and circuit recovery mechanism made a single storage node have the ability to resist single-event flipping.The single-event flipping capability of the trigger was tested by Spectre simulation.The D flip-flop can make the whole chip have anti-single-event effect without affecting the design flow,and effectively improve the problem that the chip area is greatly improved due to the introduction of radiation-proof design.The main research contents are as follows:1: Establishing a 3D device model using Synopsy'sSentauraus software,based on foundry's PDK and SPICE models,to determine the device's minimum size,spacing,STI depth and other design rules to establish a 90 nm process PMOS 3D model.2: An error detection circuit composed of a plurality of NAND gate logic units is proposed,which is mainly used for detecting a single event effect(SEE)occurring in a combinational logic circuit under 65 nm technology process.The TCAD and circuit hybrid simulation are used to simulate and evaluate the propagation effects produced by single-event upset(SEU)in logic circuits.The results show that the circuit design can reduce the incidence of soft errors in insensitive periodic signals,and the circuit does not cause significant changes in the area and operation speed of the chip.3: This article provides a D flip-flop that is resistant to single-event flipping.Mainly through the dual-mode redundancy reinforcement of the master latch and the slave latch,adding the buffer circuit before the master latch and the slave latch,and fully supporting the DICE structure in circuits such as buffers and latches.Application,finally achieve high reliability anti-single-particle flip function,and use 3D device model and SPICE parameter model for hybrid simulation of devices and circuits.Device simulation is used for C-cell structure in master-slave latches,and other units use circuit simulation.Simulation show the change of voltage and current at various points in the circuit when high-energy particles bombard the device,which proves that the new reinforced trigger structure has better radiation resistance.Finally,this paper looks forward to the application of this new type of reinforced trigger in a smaller process size.