Research On Radiation-Hardened SRAM Cell Based On 65nm Bulk CMOS Process

Nowadays,with the rapid development of integrated circuit?IC?industry,the technological process is scaling and the demand for circuit performance and reliability of devices is getting higher However,the radiation environment faced by cutting-edge fields such as aerospace,national defense and military industry is becoming more and more complex and changeable,which makes it necessary and urgent to design anti-radiation circuits for IC devices.Among them,Static Random-Access Memory?SRAM?has become an important part of IC because of its special performance and demand,and occupies a large proportion of circuit's area.At the same time,the SRAM cell is sensitive to single event effect?SEE?because of its own structure.Therefore,the design of radiation hardening for SRAM units is particularly significant.The Quatro-10T cell as the representative structure of irradiation SRAM,is widely used in the field of radiation resistance because of its good performance,but it still has a lot of room for improvement.This paper optimized and proposed a new SRAM unit based on it The main work of this paper is as follows:?1?Based on the classical Quatro-10T cell structure,a novel SRAM unit?RHBQ?with bulk silicon process read-write separation mode is proposed in this paper.At the circuit level,the grid isolation mode of double-ended writing and single-ended reading is adopted,which greatly improves the reading noise tolerance while guaranteeing the writing speed.Moreover,the use of single-ended reading lines reduces the switching power consumption of memory cells?the main part of dynamic power consumption?;at the layout level,stacked PMOS transistors are used to ensure the same driving capacity and area size.Because of the introduction of source isolation technology,the memory cell has a significantly more efficient anti-SEE capability than the classical Quatro-10T structure?2?Based on TSMC 65nm process,circuit simulation with Cadence software showed that the read-write margin of RHBQ unit proposed in this paper has been significantly improved.Compared with classical Quatro-10T,the write speed and Write Margin?WM?of RHBQ unit are increased by 44%and 141%under the conventional conditions of PVT?process,Voltage,Temperature?as TT process angle,1.2V and 27?,respectively.Read Static Noise Margin?RSNM?is increased by 58.8%,static power consumption is reduced by about 10%,and dynamic power consumption is reduced by about 76.1%.?3?Using SMIC 65nm bulk silicon process,combined with SPICE and Sentaurus TCAD mixed simulation results show that,due to the optimization of the internal topology of memory cell,under heavy particle conventional hit?vertical ion striking?,no storage data flip will occur until LET = 120MeV-cm₂/mg,and it can basically tolerate any Single Event Upset?SEU?of single node,while the sensitive nodes of Quatro-10T cell only flip between 1.1MeV-cm₂/mg and 1.2MeV-cm₂/mg.In the case of Single Event Multiple-Node Upset?SEMNU?,the charge sharing effect is taken into account.By adjusting the incident angle of particles,it is proved that RHBQ still does not have storage data flip until the LET reaches 60MeV-cm₂/mg.Thus,compared with Quatro-10T SRAM,the radiation hardening performance of RHBQ SRAM proposed in this paper has been effectively improved.